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author | Lisa Hsu <hsul@eecs.umich.edu> | 2008-11-02 21:56:57 -0500 |
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committer | Lisa Hsu <hsul@eecs.umich.edu> | 2008-11-02 21:56:57 -0500 |
commit | c55a467a06eaa59c47c52a2adddc266b8e545589 (patch) | |
tree | e86f0c75e6009285507cd2414b829c122bb0be1f /src/cpu/o3/fetch_impl.hh | |
parent | f4bceb9760c93d3b5ff3c2606f7e460b42724670 (diff) | |
download | gem5-c55a467a06eaa59c47c52a2adddc266b8e545589.tar.xz |
make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered
across the subclasses. generally make it so that member data is _cpuId and
accessor functions are cpuId(). The ID val comes from the python (default -1 if
none provided), and if it is -1, the index of cpuList will be given. this has
passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard
switch.
Diffstat (limited to 'src/cpu/o3/fetch_impl.hh')
-rw-r--r-- | src/cpu/o3/fetch_impl.hh | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 0b5ce9380..35031663e 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -593,7 +593,7 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid // Set the appropriate read size and flags as well. // Build request here. RequestPtr mem_req = new Request(tid, block_PC, cacheBlkSize, 0, - fetch_PC, cpu->readCpuId(), tid); + fetch_PC, cpu->cpuId(), tid); memReq[tid] = mem_req; |