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author | Kevin Lim <ktlim@umich.edu> | 2006-07-12 15:24:27 -0400 |
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committer | Kevin Lim <ktlim@umich.edu> | 2006-07-12 15:24:27 -0400 |
commit | 6d120b7912e554aaa44e28d1133f4bbfd9d04f66 (patch) | |
tree | f0339a87984f0927afa88edcc0561d0c69be35de /src/cpu/o3/fetch_impl.hh | |
parent | 0b0cb2bca71acdab4a30acc639509030631f9dfd (diff) | |
download | gem5-6d120b7912e554aaa44e28d1133f4bbfd9d04f66.tar.xz |
Track the PC of the cache data stored in fetch so it doesn't access memory multiple times if information is already in fetch.
--HG--
extra : convert_revision : 00b160b255e998cf99286bcc21894110c7642624
Diffstat (limited to 'src/cpu/o3/fetch_impl.hh')
-rw-r--r-- | src/cpu/o3/fetch_impl.hh | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index de883b5ba..a430f4472 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -517,6 +517,11 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid // Align the fetch PC so it's at the start of a cache block. fetch_PC = icacheBlockAlignPC(fetch_PC); + // If we've already got the block, no need to try to fetch it again. + if (fetch_PC == cacheDataPC[tid]) { + return true; + } + // Setup the memReq to do a read of the first instruction's address. // Set the appropriate read size and flags as well. // Build request here. @@ -550,6 +555,8 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid Packet::ReadReq, Packet::Broadcast); data_pkt->dataStatic(cacheData[tid]); + cacheDataPC[tid] = fetch_PC; + DPRINTF(Fetch, "Fetch: Doing instruction read.\n"); fetchedCacheLines++; |