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author | Korey Sewell <ksewell@umich.edu> | 2009-04-18 10:42:29 -0400 |
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committer | Korey Sewell <ksewell@umich.edu> | 2009-04-18 10:42:29 -0400 |
commit | 5c1742b822c1f4d640d30963a908386caf8c4a6e (patch) | |
tree | 9c4ac07248378ef4b12799d19ddc65e18d9a6f5a /src/cpu/o3/fetch_impl.hh | |
parent | cc9e834e931ff70b683b8a7010269d32c0de20fd (diff) | |
download | gem5-5c1742b822c1f4d640d30963a908386caf8c4a6e.tar.xz |
o3-delay-slot-bpred: fix decode stage handling of uncdtl. branches.\n decode stage was not setting the predicted PC correctly or passing that information back to fetch correctly
Diffstat (limited to 'src/cpu/o3/fetch_impl.hh')
-rw-r--r-- | src/cpu/o3/fetch_impl.hh | 16 |
1 files changed, 9 insertions, 7 deletions
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index c3be74234..279d3e56a 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -524,12 +524,13 @@ DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC, Addr pred_PC = next_PC; predict_taken = branchPred.predict(inst, pred_PC, tid); -/* if (predict_taken) { - DPRINTF(Fetch, "[tid:%i]: Branch predicted to be taken to %#x.\n", - tid, pred_PC); + if (predict_taken) { + DPRINTF(Fetch, "[tid:%i]: [sn:%i]: Branch predicted to be taken to %#x.\n", + tid, inst->seqNum, pred_PC); } else { - DPRINTF(Fetch, "[tid:%i]: Branch predicted to be not taken.\n", tid); - }*/ + DPRINTF(Fetch, "[tid:%i]: [sn:%i]:Branch predicted to be not taken.\n", + tid, inst->seqNum); + } #if ISA_HAS_DELAY_SLOT next_PC = next_NPC; @@ -544,8 +545,9 @@ DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC, next_PC += instSize; next_NPC = next_PC + instSize; #endif -/* DPRINTF(Fetch, "[tid:%i]: Branch predicted to go to %#x and then %#x.\n", - tid, next_PC, next_NPC);*/ + + DPRINTF(Fetch, "[tid:%i]: [sn:%i] Branch predicted to go to %#x and then %#x.\n", + tid, inst->seqNum, next_PC, next_NPC); inst->setPredTarg(next_PC, next_NPC, next_MicroPC); inst->setPredTaken(predict_taken); |