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authorKevin Lim <ktlim@umich.edu>2006-06-12 19:04:42 -0400
committerKevin Lim <ktlim@umich.edu>2006-06-12 19:04:42 -0400
commit4acb283496c7667bf0161f45e578c702d2cf8dbc (patch)
tree43a88dbf3a835170f685cc95c2ca315c6a1d710b /src/cpu/o3/fetch_impl.hh
parentfbf3a82c5c358d75acd9a97ad1dcef9796b83c96 (diff)
downloadgem5-4acb283496c7667bf0161f45e578c702d2cf8dbc.tar.xz
Clean up/shift some code around.
src/cpu/base_dyn_inst.cc: Clean up some code and update. src/cpu/base_dyn_inst.hh: Clean up some code and update with more descriptive function names. src/cpu/o3/alpha_cpu_builder.cc: src/cpu/o3/alpha_params.hh: src/cpu/o3/commit.hh: Remove unused parameters. src/cpu/o3/commit_impl.hh: Remove unused parameters, also set squashCounter directly to the counted number of squashes. src/cpu/o3/fetch_impl.hh: Update for function name changes. src/cpu/o3/iew.hh: src/cpu/o3/iew_impl.hh: Remove unused parameter, move some code into a function. --HG-- extra : convert_revision : 45abd77ad43dde2e93c2e53c4738c90ba8352a1d
Diffstat (limited to 'src/cpu/o3/fetch_impl.hh')
-rw-r--r--src/cpu/o3/fetch_impl.hh10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index c0a2a5d09..af2aadf09 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -817,7 +817,7 @@ DefaultFetch<Impl>::checkSignalsAndUpdate(unsigned tid)
// Check ROB squash signals from commit.
if (fromCommit->commitInfo[tid].robSquashing) {
- DPRINTF(Fetch, "[tid:%u]: ROB is still squashing Thread %u.\n", tid);
+ DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid);
// Continue to squash.
fetchStatus[tid] = Squashing;
@@ -984,11 +984,11 @@ DefaultFetch<Impl>::fetch(bool &status_change)
DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
next_PC,
inst_seq, cpu);
- instruction->setThread(tid);
+ instruction->setTid(tid);
instruction->setASID(tid);
- instruction->setState(cpu->thread[tid]);
+ instruction->setThreadState(cpu->thread[tid]);
DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x created "
"[sn:%lli]\n",
@@ -1065,11 +1065,11 @@ DefaultFetch<Impl>::fetch(bool &status_change)
next_PC,
inst_seq, cpu);
instruction->setPredTarg(next_PC + instSize);
- instruction->setThread(tid);
+ instruction->setTid(tid);
instruction->setASID(tid);
- instruction->setState(cpu->thread[tid]);
+ instruction->setThreadState(cpu->thread[tid]);
instruction->traceData = NULL;