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author | Lisa Hsu <hsul@eecs.umich.edu> | 2006-12-12 21:19:51 -0500 |
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committer | Lisa Hsu <hsul@eecs.umich.edu> | 2006-12-12 21:19:51 -0500 |
commit | 5d42fd836b88c1a234a5d7ddd768422f9878e2df (patch) | |
tree | bf0c98492bfa25e3e128a19769e9562ea3897596 /src/cpu/o3/fetch_impl.hh | |
parent | 369e10d95adb45da7a791e6e8a6a4ced64892f14 (diff) | |
parent | 6c8c86f2f97913788237f763d4810ab12730ca60 (diff) | |
download | gem5-5d42fd836b88c1a234a5d7ddd768422f9878e2df.tar.xz |
Merge zizzer:/bk/newmem
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5
--HG--
extra : convert_revision : 6e58629b1e51f1fc493a89f16c3f2e676dc5d191
Diffstat (limited to 'src/cpu/o3/fetch_impl.hh')
-rw-r--r-- | src/cpu/o3/fetch_impl.hh | 62 |
1 files changed, 32 insertions, 30 deletions
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 63d22b293..622259495 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -151,36 +151,6 @@ DefaultFetch<Impl>::DefaultFetch(Params *params) " RoundRobin,LSQcount,IQcount}\n"); } - // Size of cache block. - cacheBlkSize = 64; - - // Create mask to get rid of offset bits. - cacheBlkMask = (cacheBlkSize - 1); - - for (int tid=0; tid < numThreads; tid++) { - - fetchStatus[tid] = Running; - - priorityList.push_back(tid); - - memReq[tid] = NULL; - - // Create space to store a cache line. - cacheData[tid] = new uint8_t[cacheBlkSize]; - cacheDataPC[tid] = 0; - cacheDataValid[tid] = false; - - delaySlotInfo[tid].branchSeqNum = -1; - delaySlotInfo[tid].numInsts = 0; - delaySlotInfo[tid].targetAddr = 0; - delaySlotInfo[tid].targetReady = false; - - stalls[tid].decode = false; - stalls[tid].rename = false; - stalls[tid].iew = false; - stalls[tid].commit = false; - } - // Get the size of an instruction. instSize = sizeof(TheISA::MachInst); } @@ -353,6 +323,36 @@ DefaultFetch<Impl>::initStage() nextNPC[tid] = cpu->readNextNPC(tid); #endif } + + // Size of cache block. + cacheBlkSize = icachePort->peerBlockSize(); + + // Create mask to get rid of offset bits. + cacheBlkMask = (cacheBlkSize - 1); + + for (int tid=0; tid < numThreads; tid++) { + + fetchStatus[tid] = Running; + + priorityList.push_back(tid); + + memReq[tid] = NULL; + + // Create space to store a cache line. + cacheData[tid] = new uint8_t[cacheBlkSize]; + cacheDataPC[tid] = 0; + cacheDataValid[tid] = false; + + delaySlotInfo[tid].branchSeqNum = -1; + delaySlotInfo[tid].numInsts = 0; + delaySlotInfo[tid].targetAddr = 0; + delaySlotInfo[tid].targetReady = false; + + stalls[tid].decode = false; + stalls[tid].rename = false; + stalls[tid].iew = false; + stalls[tid].commit = false; + } } template<class Impl> @@ -1139,6 +1139,8 @@ DefaultFetch<Impl>::fetch(bool &status_change) ext_inst = TheISA::makeExtMI(inst, fetch_PC); #elif THE_ISA == SPARC_ISA ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC()); +#elif THE_ISA == MIPS_ISA + ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC()); #endif // Create a new DynInst from the instruction fetched. |