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| author | Ali Saidi <saidi@eecs.umich.edu> | 2007-06-01 14:18:45 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-06-01 14:18:45 -0400 |
| commit | be0aef981943d123e0f4eb8c5520a74c1eb1002a (patch) | |
| tree | 84a847d42f203bf8e5f57e19c40af37091535960 /src/cpu/o3/fetch_impl.hh | |
| parent | a7fe9345eefa106c12630eb92df5dc956d94820c (diff) | |
| parent | d8f676996222dfc2d2666bdc88499c58f1c1246c (diff) | |
| download | gem5-be0aef981943d123e0f4eb8c5520a74c1eb1002a.tar.xz | |
Merge zizzer:/bk/newmem
into zeep.pool:/z/saidi/work/m5.newmem
src/cpu/simple/base.cc:
hand merge vincent/gabe/my changes to cast sizeof() to a 64bit int
--HG--
extra : convert_revision : eb989b4d65d08057df1777c04b8ee2cfa75a2695
Diffstat (limited to 'src/cpu/o3/fetch_impl.hh')
| -rw-r--r-- | src/cpu/o3/fetch_impl.hh | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index e16f97558..895b4a46c 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -1151,10 +1151,14 @@ DefaultFetch<Impl>::fetch(bool &status_change) DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n", tid, instruction->staticInst->disassemble(fetch_PC)); +#if TRACING_ON instruction->traceData = Trace::getInstRecord(curTick, cpu->tcBase(tid), instruction->staticInst, instruction->readPC()); +#elif + instruction->traceData = NULL; +#endif ///FIXME This needs to be more robust in dealing with delay slots #if !ISA_HAS_DELAY_SLOT |