Merge zizzer:/bk/sparcfs

into  zed.eecs.umich.edu:/z/hsul/work/m5/newmem

--HG--
extra : convert_revision : 92a865a90a7c3e251ed1443f79640f761b359c1d

1 files changed, 32 insertions, 30 deletions

diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 63d22b293..622259495 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -151,36 +151,6 @@ DefaultFetch<Impl>::DefaultFetch(Params *params)
               " RoundRobin,LSQcount,IQcount}\n");
     }
 
-    // Size of cache block.
-    cacheBlkSize = 64;
-
-    // Create mask to get rid of offset bits.
-    cacheBlkMask = (cacheBlkSize - 1);
-
-    for (int tid=0; tid < numThreads; tid++) {
-
-        fetchStatus[tid] = Running;
-
-        priorityList.push_back(tid);
-
-        memReq[tid] = NULL;
-
-        // Create space to store a cache line.
-        cacheData[tid] = new uint8_t[cacheBlkSize];
-        cacheDataPC[tid] = 0;
-        cacheDataValid[tid] = false;
-
-        delaySlotInfo[tid].branchSeqNum = -1;
-        delaySlotInfo[tid].numInsts = 0;
-        delaySlotInfo[tid].targetAddr = 0;
-        delaySlotInfo[tid].targetReady = false;
-
-        stalls[tid].decode = false;
-        stalls[tid].rename = false;
-        stalls[tid].iew = false;
-        stalls[tid].commit = false;
-    }
-
     // Get the size of an instruction.
     instSize = sizeof(TheISA::MachInst);
 }
@@ -353,6 +323,36 @@ DefaultFetch<Impl>::initStage()
         nextNPC[tid] = cpu->readNextNPC(tid);
 #endif
     }
+
+    // Size of cache block.
+    cacheBlkSize = icachePort->peerBlockSize();
+
+    // Create mask to get rid of offset bits.
+    cacheBlkMask = (cacheBlkSize - 1);
+
+    for (int tid=0; tid < numThreads; tid++) {
+
+        fetchStatus[tid] = Running;
+
+        priorityList.push_back(tid);
+
+        memReq[tid] = NULL;
+
+        // Create space to store a cache line.
+        cacheData[tid] = new uint8_t[cacheBlkSize];
+        cacheDataPC[tid] = 0;
+        cacheDataValid[tid] = false;
+
+        delaySlotInfo[tid].branchSeqNum = -1;
+        delaySlotInfo[tid].numInsts = 0;
+        delaySlotInfo[tid].targetAddr = 0;
+        delaySlotInfo[tid].targetReady = false;
+
+        stalls[tid].decode = false;
+        stalls[tid].rename = false;
+        stalls[tid].iew = false;
+        stalls[tid].commit = false;
+    }
 }
 
 template<class Impl>
@@ -1139,6 +1139,8 @@ DefaultFetch<Impl>::fetch(bool &status_change)
             ext_inst = TheISA::makeExtMI(inst, fetch_PC);
 #elif THE_ISA == SPARC_ISA
             ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC());
+#elif THE_ISA == MIPS_ISA
+            ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC());
 #endif
 
             // Create a new DynInst from the instruction fetched.