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author | Mitch Hayenga <mitch.hayenga@arm.com> | 2014-09-20 17:18:35 -0400 |
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committer | Mitch Hayenga <mitch.hayenga@arm.com> | 2014-09-20 17:18:35 -0400 |
commit | e1403fc2af61c224c573c47c77a36f9b1b78e7df (patch) | |
tree | 07647bb8697ac256d180bf8de35080eee2a63f3e /src/cpu/o3/fetch_impl.hh | |
parent | 2b0438a11eb6a9640b06da91e8a300d0ac3ad81a (diff) | |
download | gem5-e1403fc2af61c224c573c47c77a36f9b1b78e7df.tar.xz |
alpha,arm,mips,power,x86,cpu,sim: Cleanup activate/deactivate
activate(), suspend(), and halt() used on thread contexts had an optional
delay parameter. However this parameter was often ignored. Also, when used,
the delay was seemily arbitrarily set to 0 or 1 cycle (no other delays were
ever specified). This patch removes the delay parameter and 'Events'
associated with them across all ISAs and cores. Unused activate logic
is also removed.
Diffstat (limited to 'src/cpu/o3/fetch_impl.hh')
-rw-r--r-- | src/cpu/o3/fetch_impl.hh | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index b9e3b78c5..7319b38a5 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -811,10 +811,7 @@ DefaultFetch<Impl>::checkStall(ThreadID tid) const { bool ret_val = false; - if (cpu->contextSwitch) { - DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid); - ret_val = true; - } else if (stalls[tid].drain) { + if (stalls[tid].drain) { assert(cpu->isDraining()); DPRINTF(Fetch,"[tid:%i]: Drain stall detected.\n",tid); ret_val = true; @@ -970,9 +967,8 @@ DefaultFetch<Impl>::tick() } // If there was activity this cycle, inform the CPU of it. - if (wroteToTimeBuffer || cpu->contextSwitch) { + if (wroteToTimeBuffer) { DPRINTF(Activity, "Activity this cycle.\n"); - cpu->activityThisCycle(); } |