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authorRekai Gonzalez-Alberquilla <rekai.gonzalezalberquilla@arm.com>2017-02-10 17:30:22 +0000
committerGiacomo Gabrielli <giacomo.gabrielli@arm.com>2018-11-28 14:12:35 +0000
commit3bb49cb2b01e55e33cd2ca7a872be65c49fabfc6 (patch)
treebb90dca9ef7fc42df1869eeaba8fce9d41c32926 /src/cpu/o3/fetch_impl.hh
parentc918d1435c243f2c74969b35793a87e10796c1a6 (diff)
downloadgem5-3bb49cb2b01e55e33cd2ca7a872be65c49fabfc6.tar.xz
cpu,arch-arm: Initialise data members
The value that is not initialized has a bogus value that manifests when using some debug-flags what makes the usage of tracediff a bit more challenging. In addition, while debugging with other techniques, it introduces the problem of understanding if the value of a field is 'intended' or just an effect of the lack of initialisation. Change-Id: Ied88caa77479c6f1d5166d80d1a1a057503cb106 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13125 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/cpu/o3/fetch_impl.hh')
-rw-r--r--src/cpu/o3/fetch_impl.hh12
1 files changed, 11 insertions, 1 deletions
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 5810c032f..537f93089 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -80,6 +80,7 @@ using namespace std;
template<class Impl>
DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params)
: cpu(_cpu),
+ branchPred(nullptr),
decodeToFetchDelay(params->decodeToFetchDelay),
renameToFetchDelay(params->renameToFetchDelay),
iewToFetchDelay(params->iewToFetchDelay),
@@ -143,10 +144,19 @@ DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params)
instSize = sizeof(TheISA::MachInst);
for (int i = 0; i < Impl::MaxThreads; i++) {
- decoder[i] = NULL;
+ fetchStatus[i] = Idle;
+ decoder[i] = nullptr;
+ pc[i] = 0;
+ fetchOffset[i] = 0;
+ macroop[i] = nullptr;
+ delayedCommit[i] = false;
+ memReq[i] = nullptr;
+ stalls[i] = {false, false};
fetchBuffer[i] = NULL;
fetchBufferPC[i] = 0;
fetchBufferValid[i] = false;
+ lastIcacheStall[i] = 0;
+ issuePipelinedIfetch[i] = false;
}
branchPred = params->branchPred;