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authorGabe Black <gblack@eecs.umich.edu>2009-02-25 10:15:44 -0800
committerGabe Black <gblack@eecs.umich.edu>2009-02-25 10:15:44 -0800
commit5605079b1f20bc7f6a4a80c8d1e4daabe7125270 (patch)
tree29dfa1685e3e257e3857ef7f9672778d43582440 /src/cpu/o3/fetch_impl.hh
parenta1aba01a02a8c1261120de83d8fbfd6624f0cb17 (diff)
downloadgem5-5605079b1f20bc7f6a4a80c8d1e4daabe7125270.tar.xz
ISA: Replace the translate functions in the TLBs with translateAtomic.
Diffstat (limited to 'src/cpu/o3/fetch_impl.hh')
-rw-r--r--src/cpu/o3/fetch_impl.hh2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 4beb34a85..06df46c2b 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -599,7 +599,7 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid
memReq[tid] = mem_req;
// Translate the instruction request.
- fault = cpu->itb->translate(mem_req, cpu->thread[tid]->getTC());
+ fault = cpu->itb->translateAtomic(mem_req, cpu->thread[tid]->getTC());
// In the case of faults, the fetch stage may need to stall and wait
// for the ITB miss to be handled.