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authorNilay Vaish <nilay@cs.wisc.edu>2015-07-26 10:21:20 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2015-07-26 10:21:20 -0500
commit608641e23c7f2288810c3f23a1a63790b664f2ab (patch)
tree0656aaf9653e8d263f5daac0d5f0fe3190193ae5 /src/cpu/o3/free_list.hh
parent6e354e82d9395b20f5f148cd545d0666b626e8ac (diff)
downloadgem5-608641e23c7f2288810c3f23a1a63790b664f2ab.tar.xz
cpu: implements vector registers
This adds a vector register type. The type is defined as a std::array of a fixed number of uint64_ts. The isa_parser.py has been modified to parse vector register operands and generate the required code. Different cpus have vector register files now.
Diffstat (limited to 'src/cpu/o3/free_list.hh')
-rw-r--r--src/cpu/o3/free_list.hh21
1 files changed, 19 insertions, 2 deletions
diff --git a/src/cpu/o3/free_list.hh b/src/cpu/o3/free_list.hh
index aa805e26e..d345d7ac8 100644
--- a/src/cpu/o3/free_list.hh
+++ b/src/cpu/o3/free_list.hh
@@ -109,6 +109,9 @@ class UnifiedFreeList
/** The list of free condition-code registers. */
SimpleFreeList ccList;
+ /** The list of free vector registers. */
+ SimpleFreeList vectorList;
+
/**
* The register file object is used only to distinguish integer
* from floating-point physical register indices.
@@ -148,6 +151,9 @@ class UnifiedFreeList
/** Gets a free cc register. */
PhysRegIndex getCCReg() { return ccList.getReg(); }
+ /** Gets a free vector register. */
+ PhysRegIndex getVectorReg() { return vectorList.getReg(); }
+
/** Adds a register back to the free list. */
void addReg(PhysRegIndex freed_reg);
@@ -160,6 +166,9 @@ class UnifiedFreeList
/** Adds a cc register back to the free list. */
void addCCReg(PhysRegIndex freed_reg) { ccList.addReg(freed_reg); }
+ /** Adds a vector register back to the free list. */
+ void addVectorReg(PhysRegIndex freed_reg) { vectorList.addReg(freed_reg); }
+
/** Checks if there are any free integer registers. */
bool hasFreeIntRegs() const { return intList.hasFreeRegs(); }
@@ -169,6 +178,9 @@ class UnifiedFreeList
/** Checks if there are any free cc registers. */
bool hasFreeCCRegs() const { return ccList.hasFreeRegs(); }
+ /** Checks if there are any free vector registers. */
+ bool hasFreeVectorRegs() const { return vectorList.hasFreeRegs(); }
+
/** Returns the number of free integer registers. */
unsigned numFreeIntRegs() const { return intList.numFreeRegs(); }
@@ -177,6 +189,9 @@ class UnifiedFreeList
/** Returns the number of free cc registers. */
unsigned numFreeCCRegs() const { return ccList.numFreeRegs(); }
+
+ /** Returns the number of free vector registers. */
+ unsigned numFreeVectorRegs() const { return vectorList.numFreeRegs(); }
};
inline void
@@ -189,9 +204,11 @@ UnifiedFreeList::addReg(PhysRegIndex freed_reg)
intList.addReg(freed_reg);
} else if (regFile->isFloatPhysReg(freed_reg)) {
floatList.addReg(freed_reg);
- } else {
- assert(regFile->isCCPhysReg(freed_reg));
+ } else if (regFile->isCCPhysReg(freed_reg)) {
ccList.addReg(freed_reg);
+ } else {
+ assert(regFile->isVectorPhysReg(freed_reg));
+ vectorList.addReg(freed_reg);
}
// These assert conditions ensure that the number of free