Merge ktlim@zizzer:/bk/m5

into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem

SConstruct:
src/SConscript:
src/arch/SConscript:
src/arch/alpha/faults.cc:
src/arch/alpha/tlb.cc:
src/base/traceflags.py:
src/cpu/SConscript:
src/cpu/base.cc:
src/cpu/base.hh:
src/cpu/base_dyn_inst.cc:
src/cpu/cpu_exec_context.cc:
src/cpu/cpu_exec_context.hh:
src/cpu/exec_context.hh:
src/cpu/o3/alpha_cpu.hh:
src/cpu/o3/alpha_cpu_impl.hh:
src/cpu/o3/alpha_dyn_inst.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/regfile.hh:
src/cpu/ozone/cpu.hh:
src/cpu/simple/base.cc:
src/cpu/base_dyn_inst.hh:
src/cpu/o3/2bit_local_pred.cc:
src/cpu/o3/2bit_local_pred.hh:
src/cpu/o3/alpha_cpu.cc:
src/cpu/o3/alpha_cpu_builder.cc:
src/cpu/o3/alpha_dyn_inst.cc:
src/cpu/o3/alpha_dyn_inst_impl.hh:
src/cpu/o3/alpha_impl.hh:
src/cpu/o3/alpha_params.hh:
src/cpu/o3/bpred_unit.cc:
src/cpu/o3/bpred_unit.hh:
src/cpu/o3/bpred_unit_impl.hh:
src/cpu/o3/btb.cc:
src/cpu/o3/btb.hh:
src/cpu/o3/comm.hh:
src/cpu/o3/commit.cc:
src/cpu/o3/commit.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu_policy.hh:
src/cpu/o3/decode.cc:
src/cpu/o3/decode.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch.cc:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/free_list.cc:
src/cpu/o3/free_list.hh:
src/cpu/o3/iew.cc:
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue.cc:
src/cpu/o3/inst_queue.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/mem_dep_unit.cc:
src/cpu/o3/mem_dep_unit.hh:
src/cpu/o3/mem_dep_unit_impl.hh:
src/cpu/o3/ras.cc:
src/cpu/o3/ras.hh:
src/cpu/o3/rename.cc:
src/cpu/o3/rename.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/o3/rename_map.cc:
src/cpu/o3/rename_map.hh:
src/cpu/o3/rob.cc:
src/cpu/o3/rob.hh:
src/cpu/o3/rob_impl.hh:
src/cpu/o3/sat_counter.cc:
src/cpu/o3/sat_counter.hh:
src/cpu/o3/store_set.cc:
src/cpu/o3/store_set.hh:
src/cpu/o3/tournament_pred.cc:
src/cpu/o3/tournament_pred.hh:
    Hand merges.

--HG--
rename : build/SConstruct => SConstruct
rename : SConscript => src/SConscript
rename : arch/alpha/ev5.cc => src/arch/alpha/ev5.cc
rename : arch/alpha/isa/decoder.isa => src/arch/alpha/isa/decoder.isa
rename : arch/alpha/isa/pal.isa => src/arch/alpha/isa/pal.isa
rename : base/traceflags.py => src/base/traceflags.py
rename : cpu/SConscript => src/cpu/SConscript
rename : cpu/base.cc => src/cpu/base.cc
rename : cpu/base.hh => src/cpu/base.hh
rename : cpu/base_dyn_inst.cc => src/cpu/base_dyn_inst.cc
rename : cpu/base_dyn_inst.hh => src/cpu/base_dyn_inst.hh
rename : cpu/cpu_exec_context.cc => src/cpu/cpu_exec_context.cc
rename : cpu/cpu_exec_context.hh => src/cpu/cpu_exec_context.hh
rename : cpu/cpu_models.py => src/cpu/cpu_models.py
rename : cpu/exec_context.hh => src/cpu/exec_context.hh
rename : cpu/exetrace.cc => src/cpu/exetrace.cc
rename : cpu/exetrace.hh => src/cpu/exetrace.hh
rename : cpu/inst_seq.hh => src/cpu/inst_seq.hh
rename : cpu/o3/2bit_local_pred.cc => src/cpu/o3/2bit_local_pred.cc
rename : cpu/o3/2bit_local_pred.hh => src/cpu/o3/2bit_local_pred.hh
rename : cpu/o3/alpha_cpu.hh => src/cpu/o3/alpha_cpu.hh
rename : cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha_cpu_builder.cc
rename : cpu/o3/alpha_cpu_impl.hh => src/cpu/o3/alpha_cpu_impl.hh
rename : cpu/o3/alpha_dyn_inst.hh => src/cpu/o3/alpha_dyn_inst.hh
rename : cpu/o3/alpha_dyn_inst_impl.hh => src/cpu/o3/alpha_dyn_inst_impl.hh
rename : cpu/o3/alpha_impl.hh => src/cpu/o3/alpha_impl.hh
rename : cpu/o3/alpha_params.hh => src/cpu/o3/alpha_params.hh
rename : cpu/o3/bpred_unit.cc => src/cpu/o3/bpred_unit.cc
rename : cpu/o3/bpred_unit.hh => src/cpu/o3/bpred_unit.hh
rename : cpu/o3/bpred_unit_impl.hh => src/cpu/o3/bpred_unit_impl.hh
rename : cpu/o3/btb.cc => src/cpu/o3/btb.cc
rename : cpu/o3/btb.hh => src/cpu/o3/btb.hh
rename : cpu/o3/comm.hh => src/cpu/o3/comm.hh
rename : cpu/o3/commit.cc => src/cpu/o3/commit.cc
rename : cpu/o3/commit.hh => src/cpu/o3/commit.hh
rename : cpu/o3/commit_impl.hh => src/cpu/o3/commit_impl.hh
rename : cpu/o3/cpu.cc => src/cpu/o3/cpu.cc
rename : cpu/o3/cpu.hh => src/cpu/o3/cpu.hh
rename : cpu/o3/cpu_policy.hh => src/cpu/o3/cpu_policy.hh
rename : cpu/o3/decode.cc => src/cpu/o3/decode.cc
rename : cpu/o3/decode.hh => src/cpu/o3/decode.hh
rename : cpu/o3/decode_impl.hh => src/cpu/o3/decode_impl.hh
rename : cpu/o3/fetch.cc => src/cpu/o3/fetch.cc
rename : cpu/o3/fetch.hh => src/cpu/o3/fetch.hh
rename : cpu/o3/fetch_impl.hh => src/cpu/o3/fetch_impl.hh
rename : cpu/o3/free_list.cc => src/cpu/o3/free_list.cc
rename : cpu/o3/free_list.hh => src/cpu/o3/free_list.hh
rename : cpu/o3/iew.cc => src/cpu/o3/iew.cc
rename : cpu/o3/iew.hh => src/cpu/o3/iew.hh
rename : cpu/o3/iew_impl.hh => src/cpu/o3/iew_impl.hh
rename : cpu/o3/inst_queue.cc => src/cpu/o3/inst_queue.cc
rename : cpu/o3/inst_queue.hh => src/cpu/o3/inst_queue.hh
rename : cpu/o3/inst_queue_impl.hh => src/cpu/o3/inst_queue_impl.hh
rename : cpu/o3/mem_dep_unit.cc => src/cpu/o3/mem_dep_unit.cc
rename : cpu/o3/mem_dep_unit.hh => src/cpu/o3/mem_dep_unit.hh
rename : cpu/o3/mem_dep_unit_impl.hh => src/cpu/o3/mem_dep_unit_impl.hh
rename : cpu/o3/ras.cc => src/cpu/o3/ras.cc
rename : cpu/o3/ras.hh => src/cpu/o3/ras.hh
rename : cpu/o3/regfile.hh => src/cpu/o3/regfile.hh
rename : cpu/o3/rename.cc => src/cpu/o3/rename.cc
rename : cpu/o3/rename.hh => src/cpu/o3/rename.hh
rename : cpu/o3/rename_impl.hh => src/cpu/o3/rename_impl.hh
rename : cpu/o3/rename_map.cc => src/cpu/o3/rename_map.cc
rename : cpu/o3/rename_map.hh => src/cpu/o3/rename_map.hh
rename : cpu/o3/rob.hh => src/cpu/o3/rob.hh
rename : cpu/o3/rob_impl.hh => src/cpu/o3/rob_impl.hh
rename : cpu/o3/sat_counter.hh => src/cpu/o3/sat_counter.hh
rename : cpu/o3/store_set.cc => src/cpu/o3/store_set.cc
rename : cpu/o3/store_set.hh => src/cpu/o3/store_set.hh
rename : cpu/o3/tournament_pred.cc => src/cpu/o3/tournament_pred.cc
rename : cpu/o3/tournament_pred.hh => src/cpu/o3/tournament_pred.hh
rename : cpu/ozone/cpu.cc => src/cpu/ozone/cpu.cc
rename : cpu/ozone/cpu.hh => src/cpu/ozone/cpu.hh
rename : cpu/ozone/cpu_impl.hh => src/cpu/ozone/cpu_impl.hh
rename : cpu/static_inst.hh => src/cpu/static_inst.hh
rename : kern/system_events.cc => src/kern/system_events.cc
rename : kern/tru64/tru64.hh => src/kern/tru64/tru64.hh
rename : python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/AlphaFullCPU.py
rename : sim/pseudo_inst.cc => src/sim/pseudo_inst.cc
extra : convert_revision : ff351fc0e3a7c0f23e59fdbec33d8209eb9280be

1 files changed, 312 insertions, 50 deletions

diff --git a/src/cpu/o3/iew.hh b/src/cpu/o3/iew.hh
index 1e370d4e6..935320628 100644
--- a/src/cpu/o3/iew.hh
+++ b/src/cpu/o3/iew.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -26,22 +26,41 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-//Todo: Update with statuses.
-//Need to handle delaying writes to the writeback bus if it's full at the
-//given time.
-
-#ifndef __CPU_O3_CPU_SIMPLE_IEW_HH__
-#define __CPU_O3_CPU_SIMPLE_IEW_HH__
+#ifndef __CPU_O3_IEW_HH__
+#define __CPU_O3_IEW_HH__
 
 #include <queue>
 
-#include "config/full_system.hh"
 #include "base/statistics.hh"
 #include "base/timebuf.hh"
+#include "config/full_system.hh"
 #include "cpu/o3/comm.hh"
-
+#include "cpu/o3/scoreboard.hh"
+#include "cpu/o3/lsq.hh"
+
+class FUPool;
+
+/**
+ * DefaultIEW handles both single threaded and SMT IEW
+ * (issue/execute/writeback).  It handles the dispatching of
+ * instructions to the LSQ/IQ as part of the issue stage, and has the
+ * IQ try to issue instructions each cycle. The execute latency is
+ * actually tied into the issue latency to allow the IQ to be able to
+ * do back-to-back scheduling without having to speculatively schedule
+ * instructions. This happens by having the IQ have access to the
+ * functional units, and the IQ gets the execution latencies from the
+ * FUs when it issues instructions. Instructions reach the execute
+ * stage on the last cycle of their execution, which is when the IQ
+ * knows to wake up any dependent instructions, allowing back to back
+ * scheduling. The execute portion of IEW separates memory
+ * instructions from non-memory instructions, either telling the LSQ
+ * to execute the instruction, or executing the instruction directly.
+ * The writeback portion of IEW completes the instructions by waking
+ * up any dependents, and marking the register ready on the
+ * scoreboard.
+ */
 template<class Impl>
-class SimpleIEW
+class DefaultIEW
 {
   private:
     //Typedefs from Impl
@@ -52,7 +71,7 @@ class SimpleIEW
 
     typedef typename CPUPol::IQ IQ;
     typedef typename CPUPol::RenameMap RenameMap;
-    typedef typename CPUPol::LDSTQ LDSTQ;
+    typedef typename CPUPol::LSQ LSQ;
 
     typedef typename CPUPol::TimeStruct TimeStruct;
     typedef typename CPUPol::IEWStruct IEWStruct;
@@ -60,77 +79,222 @@ class SimpleIEW
     typedef typename CPUPol::IssueStruct IssueStruct;
 
     friend class Impl::FullCPU;
+    friend class CPUPol::IQ;
+
   public:
+    /** Overall IEW stage status. Used to determine if the CPU can
+     * deschedule itself due to a lack of activity.
+     */
     enum Status {
+        Active,
+        Inactive
+    };
+
+    /** Status for Issue, Execute, and Writeback stages. */
+    enum StageStatus {
         Running,
         Blocked,
         Idle,
+        StartSquash,
         Squashing,
         Unblocking
     };
 
   private:
+    /** Overall stage status. */
     Status _status;
-    Status _issueStatus;
-    Status _exeStatus;
-    Status _wbStatus;
+    /** Dispatch status. */
+    StageStatus dispatchStatus[Impl::MaxThreads];
+    /** Execute status. */
+    StageStatus exeStatus;
+    /** Writeback status. */
+    StageStatus wbStatus;
 
   public:
-    class WritebackEvent : public Event {
+    /** LdWriteback event for a load completion. */
+    class LdWritebackEvent : public Event {
       private:
+        /** Instruction that is writing back data to the register file. */
         DynInstPtr inst;
-        SimpleIEW<Impl> *iewStage;
+        /** Pointer to IEW stage. */
+        DefaultIEW<Impl> *iewStage;
 
       public:
-        WritebackEvent(DynInstPtr &_inst, SimpleIEW<Impl> *_iew);
+        /** Constructs a load writeback event. */
+        LdWritebackEvent(DynInstPtr &_inst, DefaultIEW<Impl> *_iew);
 
+        /** Processes writeback event. */
         virtual void process();
+        /** Returns the description of the writeback event. */
         virtual const char *description();
     };
 
   public:
-    SimpleIEW(Params &params);
+    /** Constructs a DefaultIEW with the given parameters. */
+    DefaultIEW(Params *params);
+
+    /** Returns the name of the DefaultIEW stage. */
+    std::string name() const;
 
+    /** Registers statistics. */
     void regStats();
 
+    /** Initializes stage; sends back the number of free IQ and LSQ entries. */
+    void initStage();
+
+    /** Sets CPU pointer for IEW, IQ, and LSQ. */
     void setCPU(FullCPU *cpu_ptr);
 
+    /** Sets main time buffer used for backwards communication. */
     void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
 
+    /** Sets time buffer for getting instructions coming from rename. */
     void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
 
+    /** Sets time buffer to pass on instructions to commit. */
     void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
 
-    void setRenameMap(RenameMap *rm_ptr);
+    /** Sets pointer to list of active threads. */
+    void setActiveThreads(std::list<unsigned> *at_ptr);
+
+    /** Sets pointer to the scoreboard. */
+    void setScoreboard(Scoreboard *sb_ptr);
+
+    void switchOut();
 
-    void squash();
+    void doSwitchOut();
 
-    void squashDueToBranch(DynInstPtr &inst);
+    void takeOverFrom();
 
-    void squashDueToMem(DynInstPtr &inst);
+    bool isSwitchedOut() { return switchedOut; }
 
-    void block();
+    /** Sets page table pointer within LSQ. */
+//    void setPageTable(PageTable *pt_ptr);
 
-    inline void unblock();
+    /** Squashes instructions in IEW for a specific thread. */
+    void squash(unsigned tid);
 
+    /** Wakes all dependents of a completed instruction. */
     void wakeDependents(DynInstPtr &inst);
 
+    /** Tells memory dependence unit that a memory instruction needs to be
+     * rescheduled. It will re-execute once replayMemInst() is called.
+     */
+    void rescheduleMemInst(DynInstPtr &inst);
+
+    /** Re-executes all rescheduled memory instructions. */
+    void replayMemInst(DynInstPtr &inst);
+
+    /** Sends an instruction to commit through the time buffer. */
     void instToCommit(DynInstPtr &inst);
 
+    /** Inserts unused instructions of a thread into the skid buffer. */
+    void skidInsert(unsigned tid);
+
+    /** Returns the max of the number of entries in all of the skid buffers. */
+    int skidCount();
+
+    /** Returns if all of the skid buffers are empty. */
+    bool skidsEmpty();
+
+    /** Updates overall IEW status based on all of the stages' statuses. */
+    void updateStatus();
+
+    /** Resets entries of the IQ and the LSQ. */
+    void resetEntries();
+
+    /** Tells the CPU to wakeup if it has descheduled itself due to no
+     * activity. Used mainly by the LdWritebackEvent.
+     */
+    void wakeCPU();
+
+    /** Reports to the CPU that there is activity this cycle. */
+    void activityThisCycle();
+
+    /** Tells CPU that the IEW stage is active and running. */
+    inline void activateStage();
+
+    /** Tells CPU that the IEW stage is inactive and idle. */
+    inline void deactivateStage();
+
+    /** Returns if the LSQ has any stores to writeback. */
+    bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); }
+
   private:
-    void dispatchInsts();
+    /** Sends commit proper information for a squash due to a branch
+     * mispredict.
+     */
+    void squashDueToBranch(DynInstPtr &inst, unsigned thread_id);
 
+    /** Sends commit proper information for a squash due to a memory order
+     * violation.
+     */
+    void squashDueToMemOrder(DynInstPtr &inst, unsigned thread_id);
+
+    /** Sends commit proper information for a squash due to memory becoming
+     * blocked (younger issued instructions must be retried).
+     */
+    void squashDueToMemBlocked(DynInstPtr &inst, unsigned thread_id);
+
+    /** Sets Dispatch to blocked, and signals back to other stages to block. */
+    void block(unsigned thread_id);
+
+    /** Unblocks Dispatch if the skid buffer is empty, and signals back to
+     * other stages to unblock.
+     */
+    void unblock(unsigned thread_id);
+
+    /** Determines proper actions to take given Dispatch's status. */
+    void dispatch(unsigned tid);
+
+    /** Dispatches instructions to IQ and LSQ. */
+    void dispatchInsts(unsigned tid);
+
+    /** Executes instructions. In the case of memory operations, it informs the
+     * LSQ to execute the instructions. Also handles any redirects that occur
+     * due to the executed instructions.
+     */
     void executeInsts();
 
+    /** Writebacks instructions. In our model, the instruction's execute()
+     * function atomically reads registers, executes, and writes registers.
+     * Thus this writeback only wakes up dependent instructions, and informs
+     * the scoreboard of registers becoming ready.
+     */
+    void writebackInsts();
+
+    /** Returns the number of valid, non-squashed instructions coming from
+     * rename to dispatch.
+     */
+    unsigned validInstsFromRename();
+
+    /** Reads the stall signals. */
+    void readStallSignals(unsigned tid);
+
+    /** Checks if any of the stall conditions are currently true. */
+    bool checkStall(unsigned tid);
+
+    /** Processes inputs and changes state accordingly. */
+    void checkSignalsAndUpdate(unsigned tid);
+
+    /** Sorts instructions coming from rename into lists separated by thread. */
+    void sortInsts();
+
   public:
+    /** Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and
+     * Writeback to run for one cycle.
+     */
     void tick();
 
-    void iew();
+  private:
+    void updateExeInstStats(DynInstPtr &inst);
 
-    //Interfaces to objects inside and outside of IEW.
-    /** Time buffer interface. */
+    /** Pointer to main time buffer used for backwards communication. */
     TimeBuffer<TimeStruct> *timeBuffer;
 
+    /** Wire to write information heading to previous stages. */
+    typename TimeBuffer<TimeStruct>::wire toFetch;
+
     /** Wire to get commit's output from backwards time buffer. */
     typename TimeBuffer<TimeStruct>::wire fromCommit;
 
@@ -158,32 +322,67 @@ class SimpleIEW
     /** Wire to write infromation heading to commit. */
     typename TimeBuffer<IEWStruct>::wire toCommit;
 
-    //Will need internal queue to hold onto instructions coming from
-    //the rename stage in case of a stall.
+    /** Queue of all instructions coming from rename this cycle. */
+    std::queue<DynInstPtr> insts[Impl::MaxThreads];
+
     /** Skid buffer between rename and IEW. */
-    std::queue<RenameStruct> skidBuffer;
+    std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];
 
-  protected:
+    /** Scoreboard pointer. */
+    Scoreboard* scoreboard;
+
+  public:
     /** Instruction queue. */
     IQ instQueue;
 
-    LDSTQ ldstQueue;
+    /** Load / store queue. */
+    LSQ ldstQueue;
 
-#if !FULL_SYSTEM
-  public:
-    void lsqWriteback();
-#endif
+    /** Pointer to the functional unit pool. */
+    FUPool *fuPool;
 
   private:
-    /** Pointer to rename map.  Might not want this stage to directly
-     *  access this though...
+    /** CPU pointer. */
+    FullCPU *cpu;
+
+    /** Records if IEW has written to the time buffer this cycle, so that the
+     * CPU can deschedule itself if there is no activity.
      */
-    RenameMap *renameMap;
+    bool wroteToTimeBuffer;
 
-    /** CPU interface. */
-    FullCPU *cpu;
+    /** Source of possible stalls. */
+    struct Stalls {
+        bool commit;
+    };
+
+    /** Stages that are telling IEW to stall. */
+    Stalls stalls[Impl::MaxThreads];
+
+    /** Debug function to print instructions that are issued this cycle. */
+    void printAvailableInsts();
+
+  public:
+    /** Records if the LSQ needs to be updated on the next cycle, so that
+     * IEW knows if there will be activity on the next cycle.
+     */
+    bool updateLSQNextCycle;
 
   private:
+    /** Records if there is a fetch redirect on this cycle for each thread. */
+    bool fetchRedirect[Impl::MaxThreads];
+
+    /** Used to track if all instructions have been dispatched this cycle.
+     * If they have not, then blocking must have occurred, and the instructions
+     * would already be added to the skid buffer.
+     * @todo: Fix this hack.
+     */
+    bool dispatchedAllInsts;
+
+    /** Records if the queues have been changed (inserted or issued insts),
+     * so that IEW knows to broadcast the updated amount of free entries.
+     */
+    bool updatedQueues;
+
     /** Commit to IEW delay, in ticks. */
     unsigned commitToIEWDelay;
 
@@ -211,29 +410,92 @@ class SimpleIEW
      */
     unsigned executeWidth;
 
-    /** Number of cycles stage has been squashing.  Used so that the stage
-     *  knows when it can start unblocking, which is when the previous stage
-     *  has received the stall signal and clears up its outputs.
+    /** Index into queue of instructions being written back. */
+    unsigned wbNumInst;
+
+    /** Cycle number within the queue of instructions being written back.
+     * Used in case there are too many instructions writing back at the current
+     * cycle and writesbacks need to be scheduled for the future. See comments
+     * in instToCommit().
      */
-    unsigned cyclesSquashing;
+    unsigned wbCycle;
+
+    /** Number of active threads. */
+    unsigned numThreads;
+
+    /** Pointer to list of active threads. */
+    std::list<unsigned> *activeThreads;
+
+    /** Maximum size of the skid buffer. */
+    unsigned skidBufferMax;
 
+    bool switchedOut;
+
+    /** Stat for total number of idle cycles. */
     Stats::Scalar<> iewIdleCycles;
+    /** Stat for total number of squashing cycles. */
     Stats::Scalar<> iewSquashCycles;
+    /** Stat for total number of blocking cycles. */
     Stats::Scalar<> iewBlockCycles;
+    /** Stat for total number of unblocking cycles. */
     Stats::Scalar<> iewUnblockCycles;
-//    Stats::Scalar<> iewWBInsts;
+    /** Stat for total number of instructions dispatched. */
     Stats::Scalar<> iewDispatchedInsts;
+    /** Stat for total number of squashed instructions dispatch skips. */
     Stats::Scalar<> iewDispSquashedInsts;
+    /** Stat for total number of dispatched load instructions. */
     Stats::Scalar<> iewDispLoadInsts;
+    /** Stat for total number of dispatched store instructions. */
     Stats::Scalar<> iewDispStoreInsts;
+    /** Stat for total number of dispatched non speculative instructions. */
     Stats::Scalar<> iewDispNonSpecInsts;
+    /** Stat for number of times the IQ becomes full. */
     Stats::Scalar<> iewIQFullEvents;
+    /** Stat for number of times the LSQ becomes full. */
+    Stats::Scalar<> iewLSQFullEvents;
+    /** Stat for total number of executed instructions. */
     Stats::Scalar<> iewExecutedInsts;
-    Stats::Scalar<> iewExecLoadInsts;
-    Stats::Scalar<> iewExecStoreInsts;
+    /** Stat for total number of executed load instructions. */
+    Stats::Vector<> iewExecLoadInsts;
+    /** Stat for total number of executed store instructions. */
+//    Stats::Scalar<> iewExecStoreInsts;
+    /** Stat for total number of squashed instructions skipped at execute. */
     Stats::Scalar<> iewExecSquashedInsts;
+    /** Stat for total number of memory ordering violation events. */
     Stats::Scalar<> memOrderViolationEvents;
+    /** Stat for total number of incorrect predicted taken branches. */
     Stats::Scalar<> predictedTakenIncorrect;
+    /** Stat for total number of incorrect predicted not taken branches. */
+    Stats::Scalar<> predictedNotTakenIncorrect;
+    /** Stat for total number of mispredicted branches detected at execute. */
+    Stats::Formula branchMispredicts;
+
+    Stats::Vector<> exeSwp;
+    Stats::Vector<> exeNop;
+    Stats::Vector<> exeRefs;
+    Stats::Vector<> exeBranches;
+
+//    Stats::Vector<> issued_ops;
+/*
+    Stats::Vector<> stat_fu_busy;
+    Stats::Vector2d<> stat_fuBusy;
+    Stats::Vector<> dist_unissued;
+    Stats::Vector2d<> stat_issued_inst_type;
+*/
+    Stats::Formula issueRate;
+    Stats::Formula iewExecStoreInsts;
+//    Stats::Formula issue_op_rate;
+//    Stats::Formula fu_busy_rate;
+
+    Stats::Vector<> iewInstsToCommit;
+    Stats::Vector<> writebackCount;
+    Stats::Vector<> producerInst;
+    Stats::Vector<> consumerInst;
+    Stats::Vector<> wbPenalized;
+
+    Stats::Formula wbRate;
+    Stats::Formula wbFanout;
+    Stats::Formula wbPenalizedRate;
 };
 
-#endif // __CPU_O3_CPU_IEW_HH__
+#endif // __CPU_O3_IEW_HH__