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author | Mitch Hayenga <mitch.hayenga@arm.com> | 2014-09-03 07:42:33 -0400 |
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committer | Mitch Hayenga <mitch.hayenga@arm.com> | 2014-09-03 07:42:33 -0400 |
commit | 976f27487b57e968a326752fcf74747427733df6 (patch) | |
tree | 16c9e61f702f21d82948b1f5b555ef1b7c543b15 /src/cpu/o3/iew.hh | |
parent | fd722946dd723bda5bd4aea5eedbda108141a550 (diff) | |
download | gem5-976f27487b57e968a326752fcf74747427733df6.tar.xz |
cpu: Change writeback modeling for outstanding instructions
As highlighed on the mailing list gem5's writeback modeling can impact
performance. This patch removes the limitation on maximum outstanding issued
instructions, however the number that can writeback in a single cycle is still
respected in instToCommit().
Diffstat (limited to 'src/cpu/o3/iew.hh')
-rw-r--r-- | src/cpu/o3/iew.hh | 53 |
1 files changed, 0 insertions, 53 deletions
diff --git a/src/cpu/o3/iew.hh b/src/cpu/o3/iew.hh index 24412e11f..3b752ac99 100644 --- a/src/cpu/o3/iew.hh +++ b/src/cpu/o3/iew.hh @@ -219,49 +219,6 @@ class DefaultIEW /** Returns if the LSQ has any stores to writeback. */ bool hasStoresToWB(ThreadID tid) { return ldstQueue.hasStoresToWB(tid); } - void incrWb(InstSeqNum &sn) - { - ++wbOutstanding; - if (wbOutstanding == wbMax) - ableToIssue = false; - DPRINTF(IEW, "wbOutstanding: %i [sn:%lli]\n", wbOutstanding, sn); - assert(wbOutstanding <= wbMax); -#ifdef DEBUG - wbList.insert(sn); -#endif - } - - void decrWb(InstSeqNum &sn) - { - if (wbOutstanding == wbMax) - ableToIssue = true; - wbOutstanding--; - DPRINTF(IEW, "wbOutstanding: %i [sn:%lli]\n", wbOutstanding, sn); - assert(wbOutstanding >= 0); -#ifdef DEBUG - assert(wbList.find(sn) != wbList.end()); - wbList.erase(sn); -#endif - } - -#ifdef DEBUG - std::set<InstSeqNum> wbList; - - void dumpWb() - { - std::set<InstSeqNum>::iterator wb_it = wbList.begin(); - while (wb_it != wbList.end()) { - cprintf("[sn:%lli]\n", - (*wb_it)); - wb_it++; - } - } -#endif - - bool canIssue() { return ableToIssue; } - - bool ableToIssue; - /** Check misprediction */ void checkMisprediction(DynInstPtr &inst); @@ -452,19 +409,9 @@ class DefaultIEW */ unsigned wbCycle; - /** Number of instructions in flight that will writeback. */ - - /** Number of instructions in flight that will writeback. */ - int wbOutstanding; - /** Writeback width. */ unsigned wbWidth; - /** Writeback width * writeback depth, where writeback depth is - * the number of cycles of writing back instructions that can be - * buffered. */ - unsigned wbMax; - /** Number of active threads. */ ThreadID numThreads; |