cpu: Fix o3 front-end pipeline interlock behavior

The o3 pipeline interlock/stall logic is incorrect.  o3 unnecessicarily stalled
fetch and decode due to later stages in the pipeline.  In general, a stage
should usually only consider if it is stalled by the adjacent, downstream stage.
Forcing stalls due to later stages creates and results in bubbles in the
pipeline.  Additionally, o3 stalled the entire frontend (fetch, decode, rename)
on a branch mispredict while the ROB is being serially walked to update the
RAT (robSquashing). Only should have stalled at rename.

1 files changed, 0 insertions, 11 deletions

diff --git a/src/cpu/o3/iew.hh b/src/cpu/o3/iew.hh
index 3b752ac99..77403b499 100644
--- a/src/cpu/o3/iew.hh
+++ b/src/cpu/o3/iew.hh
@@ -270,9 +270,6 @@ class DefaultIEW
      */
     unsigned validInstsFromRename();
 
-    /** Reads the stall signals. */
-    void readStallSignals(ThreadID tid);
-
     /** Checks if any of the stall conditions are currently true. */
     bool checkStall(ThreadID tid);
 
@@ -346,14 +343,6 @@ class DefaultIEW
      */
     bool wroteToTimeBuffer;
 
-    /** Source of possible stalls. */
-    struct Stalls {
-        bool commit;
-    };
-
-    /** Stages that are telling IEW to stall. */
-    Stalls stalls[Impl::MaxThreads];
-
     /** Debug function to print instructions that are issued this cycle. */
     void printAvailableInsts();