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| author | Kevin Lim <ktlim@umich.edu> | 2008-09-26 07:44:07 -0700 |
|---|---|---|
| committer | Kevin Lim <ktlim@umich.edu> | 2008-09-26 07:44:07 -0700 |
| commit | b7849032072ed7e93979d625cade3b384aa19948 (patch) | |
| tree | cf8f9578c9cc9b77cd99606875a366f1f303dad9 /src/cpu/o3/iew.hh | |
| parent | 712a8ee70090abc8c8c0fdb4a907e3ec419ae56e (diff) | |
| download | gem5-b7849032072ed7e93979d625cade3b384aa19948.tar.xz | |
O3CPU: Fix thread writeback logic.
Fix the logic in the LSQ that determines if there are any stores to
write back. In the commit stage, check for thread specific writebacks
instead of just any writeback.
Diffstat (limited to 'src/cpu/o3/iew.hh')
| -rw-r--r-- | src/cpu/o3/iew.hh | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/cpu/o3/iew.hh b/src/cpu/o3/iew.hh index 3caf847ed..bc60f401b 100644 --- a/src/cpu/o3/iew.hh +++ b/src/cpu/o3/iew.hh @@ -208,6 +208,9 @@ class DefaultIEW /** Returns if the LSQ has any stores to writeback. */ bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); } + /** Returns if the LSQ has any stores to writeback. */ + bool hasStoresToWB(unsigned tid) { return ldstQueue.hasStoresToWB(tid); } + void incrWb(InstSeqNum &sn) { if (++wbOutstanding == wbMax) |