diff options
author | Steve Reinhardt <steve.reinhardt@amd.com> | 2014-05-31 18:00:23 -0700 |
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committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2014-05-31 18:00:23 -0700 |
commit | 0be64ffe2f4ff8824b3084362706ffbf456ea490 (patch) | |
tree | 795d803dcfaa3b92faa1155ce2c835daf2d76290 /src/cpu/o3/iew_impl.hh | |
parent | 2a8088f5aec433b6a1a2330f4fbc29ae28b5ee73 (diff) | |
download | gem5-0be64ffe2f4ff8824b3084362706ffbf456ea490.tar.xz |
style: eliminate equality tests with true and false
Using '== true' in a boolean expression is totally redundant,
and using '== false' is pretty verbose (and arguably less
readable in most cases) compared to '!'.
It's somewhat of a pet peeve, perhaps, but I had some time
waiting for some tests to run and decided to clean these up.
Unfortunately, SLICC appears not to have the '!' operator,
so I had to leave the '== false' tests in the SLICC code.
Diffstat (limited to 'src/cpu/o3/iew_impl.hh')
-rw-r--r-- | src/cpu/o3/iew_impl.hh | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh index 3c133ff0c..644366dfc 100644 --- a/src/cpu/o3/iew_impl.hh +++ b/src/cpu/o3/iew_impl.hh @@ -487,7 +487,7 @@ DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid) DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s " "[sn:%i].\n", tid, inst->pcState(), inst->seqNum); - if (toCommit->squash[tid] == false || + if (!toCommit->squash[tid] || inst->seqNum < toCommit->squashedSeqNum[tid]) { toCommit->squash[tid] = true; toCommit->squashedSeqNum[tid] = inst->seqNum; @@ -517,7 +517,7 @@ DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid) // case the memory violator should take precedence over the branch // misprediction because it requires the violator itself to be included in // the squash. - if (toCommit->squash[tid] == false || + if (!toCommit->squash[tid] || inst->seqNum <= toCommit->squashedSeqNum[tid]) { toCommit->squash[tid] = true; @@ -538,7 +538,7 @@ DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid) { DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, " "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum); - if (toCommit->squash[tid] == false || + if (!toCommit->squash[tid] || inst->seqNum < toCommit->squashedSeqNum[tid]) { toCommit->squash[tid] = true; @@ -1314,7 +1314,7 @@ DefaultIEW<Impl>::executeInsts() } // If the store had a fault then it may not have a mem req - if (fault != NoFault || inst->readPredicate() == false || + if (fault != NoFault || !inst->readPredicate() || !inst->isStoreConditional()) { // If the instruction faulted, then we need to send it along // to commit without the instruction completing. @@ -1339,7 +1339,7 @@ DefaultIEW<Impl>::executeInsts() // will be replaced and we will lose it. if (inst->getFault() == NoFault) { inst->execute(); - if (inst->readPredicate() == false) + if (!inst->readPredicate()) inst->forwardOldRegs(); } |