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author | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2015-05-05 03:22:33 -0400 |
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committer | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2015-05-05 03:22:33 -0400 |
commit | 48281375ee23283d24cf9d7fe5f6315afdb3a6fc (patch) | |
tree | 8452e0a52752b913ac40fe9299c6d40f859d7e79 /src/cpu/o3/iew_impl.hh | |
parent | 1da634ace00dbae3165228b36655a62538c7c88d (diff) | |
download | gem5-48281375ee23283d24cf9d7fe5f6315afdb3a6fc.tar.xz |
mem, cpu: Add a separate flag for strictly ordered memory
The Request::UNCACHEABLE flag currently has two different
functions. The first, and obvious, function is to prevent the memory
system from caching data in the request. The second function is to
prevent reordering and speculation in CPU models.
This changeset gives the order/speculation requirement a separate flag
(Request::STRICT_ORDER). This flag prevents CPU models from doing the
following optimizations:
* Speculation: CPU models are not allowed to issue speculative
loads.
* Write combining: CPU models and caches are not allowed to merge
writes to the same cache line.
Note: The memory system may still reorder accesses unless the
UNCACHEABLE flag is set. It is therefore expected that the
STRICT_ORDER flag is combined with the UNCACHEABLE flag to prevent
this behavior.
Diffstat (limited to 'src/cpu/o3/iew_impl.hh')
-rw-r--r-- | src/cpu/o3/iew_impl.hh | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh index 4741df634..730eb0cfe 100644 --- a/src/cpu/o3/iew_impl.hh +++ b/src/cpu/o3/iew_impl.hh @@ -1418,9 +1418,9 @@ DefaultIEW<Impl>::writebackInsts() // Some instructions will be sent to commit without having // executed because they need commit to handle them. - // E.g. Uncached loads have not actually executed when they + // E.g. Strictly ordered loads have not actually executed when they // are first sent to commit. Instead commit must tell the LSQ - // when it's ready to execute the uncached load. + // when it's ready to execute the strictly ordered load. if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) { int dependents = instQueue.wakeDependents(inst); @@ -1522,9 +1522,10 @@ DefaultIEW<Impl>::tick() if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { //DPRINTF(IEW,"NonspecInst from thread %i",tid); - if (fromCommit->commitInfo[tid].uncached) { - instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad); - fromCommit->commitInfo[tid].uncachedLoad->setAtCommit(); + if (fromCommit->commitInfo[tid].strictlyOrdered) { + instQueue.replayMemInst( + fromCommit->commitInfo[tid].strictlyOrderedLoad); + fromCommit->commitInfo[tid].strictlyOrderedLoad->setAtCommit(); } else { instQueue.scheduleNonSpec( fromCommit->commitInfo[tid].nonSpecSeqNum); |