diff options
| author | Matt Horsnell <Matt.Horsnell@arm.com> | 2011-01-18 16:30:05 -0600 |
|---|---|---|
| committer | Matt Horsnell <Matt.Horsnell@arm.com> | 2011-01-18 16:30:05 -0600 |
| commit | 62f2097917c977335d025e230146c6eb56a9bb5d (patch) | |
| tree | 68bc1883947fb893961ea2474903ed1de1a40007 /src/cpu/o3/iew_impl.hh | |
| parent | 5ebf3b280867925917654f5362d3ece21dc2355e (diff) | |
| download | gem5-62f2097917c977335d025e230146c6eb56a9bb5d.tar.xz | |
O3: Fix mispredicts from non control instructions.
The squash inside the fetch unit should not attempt to remove them from the
branch predictor as non-control instructions are not pushed into the predictor.
Diffstat (limited to 'src/cpu/o3/iew_impl.hh')
| -rw-r--r-- | src/cpu/o3/iew_impl.hh | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh index 3f53b4197..0d58357fd 100644 --- a/src/cpu/o3/iew_impl.hh +++ b/src/cpu/o3/iew_impl.hh @@ -456,6 +456,7 @@ DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid) toCommit->squashedSeqNum[tid] = inst->seqNum; toCommit->mispredPC[tid] = inst->instAddr(); toCommit->branchMispredict[tid] = true; + toCommit->mispredictInst[tid] = inst; toCommit->branchTaken[tid] = inst->pcState().branching(); TheISA::PCState pc = inst->pcState(); |