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author | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2013-01-07 13:05:46 -0500 |
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committer | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2013-01-07 13:05:46 -0500 |
commit | f9bcf46371f27de8d22a1ecde4800b10eb5ef797 (patch) | |
tree | c9269b17b4ba5ac8d0a9ab3fa9931becd0a1ef44 /src/cpu/o3/inst_queue.hh | |
parent | 52ff37caa3dc434baa0468f13ac609430f078982 (diff) | |
download | gem5-f9bcf46371f27de8d22a1ecde4800b10eb5ef797.tar.xz |
cpu: Make sure that a drained timing CPU isn't executing ucode
Currently, the timing CPU can be in the middle of a microcode sequence
or multicycle (stayAtPC is true) instruction when it is drained. This
leads to two problems:
* When switching to a hardware virtualized CPU, we obviously can't
execute gem5 microcode.
* If stayAtPC is true we might execute half of an instruction twice
when restoring a checkpoint or switching CPUs, which leads to an
incorrect execution.
After applying this patch, the CPU will be on a proper instruction
boundary, which means that it is safe to switch to any CPU model
(including hardware virtualized ones). This changeset also fixes a bug
where the timing CPU sometimes switches out with while stayAtPC is
true, which corrupts the target state after a CPU switch or
checkpoint.
Note: This changeset removes the so_state variable from checkpoints
since the drain state isn't used anymore.
Diffstat (limited to 'src/cpu/o3/inst_queue.hh')
0 files changed, 0 insertions, 0 deletions