arch: ISA parser additions of vector registers

Reiley's update :) of the isa parser definitions. My addition of the
vector element operand concept for the ISA parser. Nathanael's modification
creating a hierarchy between vector registers and its constituencies to the
isa parser.

Some fixes/updates on top to consider instructions as vectors instead of
floating when they use the VectorRF. Some counters added to all the
models to keep faithful counts.

Change-Id: Id8f162a525240dfd7ba884c5a4d9fa69f4050101
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2706
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

1 files changed, 5 insertions, 1 deletions

diff --git a/src/cpu/o3/inst_queue.hh b/src/cpu/o3/inst_queue.hh
index 23d8d416c..64f8aa1be 100644
--- a/src/cpu/o3/inst_queue.hh
+++ b/src/cpu/o3/inst_queue.hh
@@ -543,10 +543,14 @@ class InstructionQueue
     Stats::Scalar intInstQueueWakeupAccesses;
     Stats::Scalar fpInstQueueReads;
     Stats::Scalar fpInstQueueWrites;
-    Stats::Scalar fpInstQueueWakeupQccesses;
+    Stats::Scalar fpInstQueueWakeupAccesses;
+    Stats::Scalar vecInstQueueReads;
+    Stats::Scalar vecInstQueueWrites;
+    Stats::Scalar vecInstQueueWakeupAccesses;
 
     Stats::Scalar intAluAccesses;
     Stats::Scalar fpAluAccesses;
+    Stats::Scalar vecAluAccesses;
 };
 
 #endif //__CPU_O3_INST_QUEUE_HH__