cpu: Fix cache blocked load behavior in o3 cpu

This patch fixes the load blocked/replay mechanism in the o3 cpu.  Rather than
flushing the entire pipeline, this patch replays loads once the cache becomes
unblocked.

Additionally, deferred memory instructions (loads which had conflicting stores),
when replayed would not respect the number of functional units (only respected
issue width).  This patch also corrects that.

Improvements over 20% have been observed on a microbenchmark designed to
exercise this behavior.

1 files changed, 22 insertions, 3 deletions

diff --git a/src/cpu/o3/inst_queue.hh b/src/cpu/o3/inst_queue.hh
index 212829ec1..d59d5281b 100644
--- a/src/cpu/o3/inst_queue.hh
+++ b/src/cpu/o3/inst_queue.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2012 ARM Limited
+ * Copyright (c) 2011-2012, 2014 ARM Limited
  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved.
  *
@@ -188,11 +188,16 @@ class InstructionQueue
      */
     DynInstPtr getInstToExecute();
 
-    /** Returns a memory instruction that was referred due to a delayed DTB
-     *  translation if it is now ready to execute.
+    /** Gets a memory instruction that was referred due to a delayed DTB
+     *  translation if it is now ready to execute.  NULL if none available.
      */
     DynInstPtr getDeferredMemInstToExecute();
 
+    /** Gets a memory instruction that was blocked on the cache. NULL if none
+     *  available.
+     */
+    DynInstPtr getBlockedMemInstToExecute();
+
     /**
      * Records the instruction as the producer of a register without
      * adding it to the rest of the IQ.
@@ -242,6 +247,12 @@ class InstructionQueue
      */
     void deferMemInst(DynInstPtr &deferred_inst);
 
+    /**  Defers a memory instruction when it is cache blocked. */
+    void blockMemInst(DynInstPtr &blocked_inst);
+
+    /**  Notify instruction queue that a previous blockage has resolved */
+    void cacheUnblocked();
+
     /** Indicates an ordering violation between a store and a load. */
     void violation(DynInstPtr &store, DynInstPtr &faulting_load);
 
@@ -308,6 +319,14 @@ class InstructionQueue
      */
     std::list<DynInstPtr> deferredMemInsts;
 
+    /** List of instructions that have been cache blocked. */
+    std::list<DynInstPtr> blockedMemInsts;
+
+    /** List of instructions that were cache blocked, but a retry has been seen
+     * since, so they can now be retried. May fail again go on the blocked list.
+     */
+    std::list<DynInstPtr> retryMemInsts;
+
     /**
      * Struct for comparing entries to be added to the priority queue.
      * This gives reverse ordering to the instructions in terms of