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| author | Giacomo Gabrielli <Giacomo.Gabrielli@arm.com> | 2014-01-24 15:29:30 -0600 |
|---|---|---|
| committer | Giacomo Gabrielli <Giacomo.Gabrielli@arm.com> | 2014-01-24 15:29:30 -0600 |
| commit | 3436de0c2ad467c65066e48969a7c12bdbbb3d26 (patch) | |
| tree | e02848c0958b2614a637b10bbc1d137a4abe069f /src/cpu/o3/inst_queue_impl.hh | |
| parent | 90b1775a8f87834d4c27d4c98483bb7b1e5e9679 (diff) | |
| download | gem5-3436de0c2ad467c65066e48969a7c12bdbbb3d26.tar.xz | |
cpu: Add support for Memory+Barrier instruction types in O3 cpu.
Diffstat (limited to 'src/cpu/o3/inst_queue_impl.hh')
| -rw-r--r-- | src/cpu/o3/inst_queue_impl.hh | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh index 8f0249ced..8eba028d6 100644 --- a/src/cpu/o3/inst_queue_impl.hh +++ b/src/cpu/o3/inst_queue_impl.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2012 ARM Limited + * Copyright (c) 2011-2013 ARM Limited * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved. * @@ -1157,11 +1157,17 @@ InstructionQueue<Impl>::doSquash(ThreadID tid) DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %s squashed.\n", tid, squashed_inst->seqNum, squashed_inst->pcState()); + bool is_acq_rel = squashed_inst->isMemBarrier() && + (squashed_inst->isLoad() || + (squashed_inst->isStore() && + !squashed_inst->isStoreConditional())); + // Remove the instruction from the dependency list. - if (!squashed_inst->isNonSpeculative() && - !squashed_inst->isStoreConditional() && - !squashed_inst->isMemBarrier() && - !squashed_inst->isWriteBarrier()) { + if (is_acq_rel || + (!squashed_inst->isNonSpeculative() && + !squashed_inst->isStoreConditional() && + !squashed_inst->isMemBarrier() && + !squashed_inst->isWriteBarrier())) { for (int src_reg_idx = 0; src_reg_idx < squashed_inst->numSrcRegs(); |