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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-04-13 13:59:31 +0000 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-04-13 13:59:31 +0000 |
| commit | c7f1cf1d58cf50118c18b1afc4c938eafba81492 (patch) | |
| tree | be5c82a40f629e12e88f6eb132c0fee27e352ae7 /src/cpu/o3/inst_queue_impl.hh | |
| parent | 6ec510385dd23f339f86f3ace4339c791affba89 (diff) | |
| download | gem5-c7f1cf1d58cf50118c18b1afc4c938eafba81492.tar.xz | |
Remove most of the special handling for delay slots since they have to be squashed anyway on a mispredict. This is because the NNPC value they saw when executing was incorrect.
--HG--
extra : convert_revision : b42c4eb28b4fbba66c65cbd0a5033bf886c1532d
Diffstat (limited to 'src/cpu/o3/inst_queue_impl.hh')
| -rw-r--r-- | src/cpu/o3/inst_queue_impl.hh | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh index 10c3287f2..bdf5f07aa 100644 --- a/src/cpu/o3/inst_queue_impl.hh +++ b/src/cpu/o3/inst_queue_impl.hh @@ -1005,11 +1005,7 @@ InstructionQueue<Impl>::squash(unsigned tid) // Read instruction sequence number of last instruction out of the // time buffer. -#if ISA_HAS_DELAY_SLOT - squashedSeqNum[tid] = fromCommit->commitInfo[tid].bdelayDoneSeqNum; -#else squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum; -#endif // Call doSquash if there are insts in the IQ if (count[tid] > 0) { |