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author | Iru Cai <mytbk920423@gmail.com> | 2019-05-12 16:20:05 +0800 |
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committer | Iru Cai <mytbk920423@gmail.com> | 2019-05-12 16:22:45 +0800 |
commit | d3e361f60741ea9ebea06375c8525385014dd9d2 (patch) | |
tree | 4cc8146567125ac5bc56f8cd4c9f14a8a38f9f0c /src/cpu/o3/inst_queue_impl.hh | |
parent | b0e609d5cf6961bb9b3f12065659e1c42c13ef06 (diff) | |
download | gem5-d3e361f60741ea9ebea06375c8525385014dd9d2.tar.xz |
finally runs dhrystone
Change-Id: I7466a825f8726682622d237460311a1c4b23b8ad
Diffstat (limited to 'src/cpu/o3/inst_queue_impl.hh')
-rw-r--r-- | src/cpu/o3/inst_queue_impl.hh | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh index 0a6d309fe..a30bf7f5f 100644 --- a/src/cpu/o3/inst_queue_impl.hh +++ b/src/cpu/o3/inst_queue_impl.hh @@ -1182,8 +1182,12 @@ InstructionQueue<Impl>::getDeferredMemInstToExecute() // 2. virtual fence ahead // 3. not ready to expose and gets a TLB miss // for both (2, 3) we need to restart the translation + + DPRINTF(IQ, "sn:%lli onlyWaitForFence = %d, fenceDelay = %d\n", (*it)->seqNum, (*it)->onlyWaitForFence(), (*it)->fenceDelay() ); + if ( (*it)->translationCompleted() || ((*it)->onlyWaitForFence() && !(*it)->fenceDelay()) + || ((*it)->onlyWaitForExpose() && (*it)->readyToExpose()) || (*it)->isSquashed()) { DynInstPtr mem_inst = std::move(*it); mem_inst->onlyWaitForFence(false); |