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| author | Yasuko Eckert <yasuko.eckert@amd.com> | 2013-10-15 14:22:44 -0400 |
|---|---|---|
| committer | Yasuko Eckert <yasuko.eckert@amd.com> | 2013-10-15 14:22:44 -0400 |
| commit | 2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2 (patch) | |
| tree | 040fdd5bad814d7cb7ee40934974d2b38b28d67a /src/cpu/o3/inst_queue_impl.hh | |
| parent | 552622184752dc798bc81f9b0b395db68aee9511 (diff) | |
| download | gem5-2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2.tar.xz | |
cpu: add a condition-code register class
Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
Diffstat (limited to 'src/cpu/o3/inst_queue_impl.hh')
| -rw-r--r-- | src/cpu/o3/inst_queue_impl.hh | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh index 3e3325beb..1c86b7c89 100644 --- a/src/cpu/o3/inst_queue_impl.hh +++ b/src/cpu/o3/inst_queue_impl.hh @@ -1,5 +1,6 @@ /* * Copyright (c) 2011-2012 ARM Limited + * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved. * * The license below extends only to copyright in the software and shall @@ -87,16 +88,15 @@ InstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, fuPool(params->fuPool), numEntries(params->numIQEntries), totalWidth(params->issueWidth), - numPhysIntRegs(params->numPhysIntRegs), - numPhysFloatRegs(params->numPhysFloatRegs), commitToIEWDelay(params->commitToIEWDelay) { assert(fuPool); numThreads = params->numThreads; - // Set the number of physical registers as the number of int + float - numPhysRegs = numPhysIntRegs + numPhysFloatRegs; + // Set the number of total physical registers + numPhysRegs = params->numPhysIntRegs + params->numPhysFloatRegs + + params->numPhysCCRegs; //Create an entry for each physical register within the //dependency graph. |