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author | Iru Cai <mytbk920423@gmail.com> | 2019-02-28 17:07:16 +0800 |
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committer | Iru Cai <mytbk920423@gmail.com> | 2019-03-20 14:32:29 +0800 |
commit | a17658beaacabe018be78c32aafe8415cdb16df0 (patch) | |
tree | 0432a6af261efd0ef03c318a67cf880a7461cc5d /src/cpu/o3/inst_queue_impl.hh | |
parent | 59505f7305cc3f3b7637233fd2d231bd7f561e80 (diff) | |
download | gem5-a17658beaacabe018be78c32aafe8415cdb16df0.tar.xz |
invisispec-1.0 source
Diffstat (limited to 'src/cpu/o3/inst_queue_impl.hh')
-rw-r--r-- | src/cpu/o3/inst_queue_impl.hh | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh index f70f66274..86dfd9214 100644 --- a/src/cpu/o3/inst_queue_impl.hh +++ b/src/cpu/o3/inst_queue_impl.hh @@ -1172,8 +1172,19 @@ InstructionQueue<Impl>::getDeferredMemInstToExecute() { for (ListIt it = deferredMemInsts.begin(); it != deferredMemInsts.end(); ++it) { - if ((*it)->translationCompleted() || (*it)->isSquashed()) { + // [InvisiSpec] we need to check the FenceDelay + // a load can be delayed due to + // 1. translation delay + // 2. virtual fence ahead + // 3. not ready to expose and gets a TLB miss + // for both (2, 3) we need to restart the translation + if ( (*it)->translationCompleted() + || ((*it)->onlyWaitForFence() && !(*it)->fenceDelay()) + || ((*it)->onlyWaitForExpose() && (*it)->readyToExpose()) + || (*it)->isSquashed()) { DynInstPtr mem_inst = *it; + mem_inst->onlyWaitForFence(false); + mem_inst->onlyWaitForExpose(false); deferredMemInsts.erase(it); return mem_inst; } |