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| author | Iru Cai <mytbk920423@gmail.com> | 2019-05-12 14:34:21 +0800 |
|---|---|---|
| committer | Iru Cai <mytbk920423@gmail.com> | 2019-05-12 14:34:21 +0800 |
| commit | b0e609d5cf6961bb9b3f12065659e1c42c13ef06 (patch) | |
| tree | d03553831a09a99902b8cf1f631f4e684f433425 /src/cpu/o3/lsq.hh | |
| parent | 2b62fec3590024a7ce82ef5d4647397d37ed37eb (diff) | |
| download | gem5-b0e609d5cf6961bb9b3f12065659e1c42c13ef06.tar.xz | |
only spec load when hit
Diffstat (limited to 'src/cpu/o3/lsq.hh')
| -rw-r--r-- | src/cpu/o3/lsq.hh | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh index e5c35a3a6..0e18aa145 100644 --- a/src/cpu/o3/lsq.hh +++ b/src/cpu/o3/lsq.hh @@ -136,14 +136,6 @@ class LSQ { /** [mengjia] - * Attempts to validate loads until all cache ports are used or the - * interface becomes blocked. - */ - int exposeLoads(); - /** Same as above, but only for one thread. */ - int exposeLoads(ThreadID tid); - - /** [mengjia] * attempt to update FenceDelay state for load insts */ void updateVisibleState(); |