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author | Iru Cai <mytbk920423@gmail.com> | 2019-02-28 17:07:16 +0800 |
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committer | Iru Cai <mytbk920423@gmail.com> | 2019-05-31 15:50:11 +0800 |
commit | a4c6e88d766858b675a7fd256df5a8b9a7e18ada (patch) | |
tree | a00f59eea3e87c31eb9efbce9f8d6f397ae16db2 /src/cpu/o3/lsq.hh | |
parent | 866b200c202dded37fdd857a1a42ec149bd109c9 (diff) | |
download | gem5-a4c6e88d766858b675a7fd256df5a8b9a7e18ada.tar.xz |
import invisispec-1.0 source by Mengjia Yan
The original code is at https://github.com/mjyan0720/InvisiSpec-1.0
This code is rebased on upstream gem5 commit 866b200c, which features:
- rdtscp support
- some C++ code optimizations
- newer Linux kernel version number in SE mode
Diffstat (limited to 'src/cpu/o3/lsq.hh')
-rw-r--r-- | src/cpu/o3/lsq.hh | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh index 0c93121e3..e5c35a3a6 100644 --- a/src/cpu/o3/lsq.hh +++ b/src/cpu/o3/lsq.hh @@ -134,6 +134,23 @@ class LSQ { /** Same as above, but only for one thread. */ void writebackStores(ThreadID tid); + + /** [mengjia] + * Attempts to validate loads until all cache ports are used or the + * interface becomes blocked. + */ + int exposeLoads(); + /** Same as above, but only for one thread. */ + int exposeLoads(ThreadID tid); + + /** [mengjia] + * attempt to update FenceDelay state for load insts + */ + void updateVisibleState(); + /** Same as above, but only for one thread. */ + void updateVisibleState(ThreadID tid); + + /** * Squash instructions from a thread until the specified sequence number. */ @@ -255,6 +272,10 @@ class LSQ { int numStoresToWB(ThreadID tid) { return thread[tid].numStoresToWB(); } + /** Returns the number of stores a specific thread has to write back. */ + int numLoadsToVLD(ThreadID tid) + { return thread[tid].numLoadsToVLD(); } + /** Returns if the LSQ will write back to memory this cycle. */ bool willWB(); /** Returns if the LSQ of a specific thread will write back to memory this |