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author | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2013-01-07 13:05:46 -0500 |
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committer | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2013-01-07 13:05:46 -0500 |
commit | 1814a85a055732baf98fd030441bb4c5c5db9bdc (patch) | |
tree | 33dd6adc62342a55ac3b0f4dbe9fdb9d82faa323 /src/cpu/o3/lsq.hh | |
parent | 9e8003148f78811e600e51a900f96b71cb525b60 (diff) | |
download | gem5-1814a85a055732baf98fd030441bb4c5c5db9bdc.tar.xz |
cpu: Rewrite O3 draining to avoid stopping in microcode
Previously, the O3 CPU could stop in the middle of a microcode
sequence. This patch makes sure that the pipeline stops when it has
committed a normal instruction or exited from a microcode
sequence. Additionally, it makes sure that the pipeline has no
instructions in flight when it is drained, which should make draining
more robust.
Draining is controlled in the commit stage, which checks if the next
PC after a committed instruction is in microcode. If this isn't the
case, it requests a squash of all instructions after that the
instruction that just committed and immediately signals a drain stall
to the fetch stage. The CPU then continues to execute until the
pipeline and all associated buffers are empty.
Diffstat (limited to 'src/cpu/o3/lsq.hh')
-rw-r--r-- | src/cpu/o3/lsq.hh | 18 |
1 files changed, 14 insertions, 4 deletions
diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh index 7caee86f6..6857a6aca 100644 --- a/src/cpu/o3/lsq.hh +++ b/src/cpu/o3/lsq.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011 ARM Limited + * Copyright (c) 2011-2012 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -79,8 +79,11 @@ class LSQ { /** Sets the pointer to the list of active threads. */ void setActiveThreads(std::list<ThreadID> *at_ptr); - /** Switches out the LSQ. */ - void switchOut(); + + /** Perform sanity checks after a drain. */ + void drainSanityCheck() const; + /** Has the LSQ drained? */ + bool isDrained() const; /** Takes over execution from another CPU's thread. */ void takeOverFrom(); @@ -211,6 +214,13 @@ class LSQ { */ bool isFull(ThreadID tid); + /** Returns if the LSQ is empty (both LQ and SQ are empty). */ + bool isEmpty() const; + /** Returns if all of the LQs are empty. */ + bool lqEmpty() const; + /** Returns if all of the SQs are empty. */ + bool sqEmpty() const; + /** Returns if any of the LQs are full. */ bool lqFull(); /** Returns if the LQ of a given thread is full. */ @@ -254,7 +264,7 @@ class LSQ { { return thread[tid].willWB(); } /** Returns if the cache is currently blocked. */ - bool cacheBlocked() + bool cacheBlocked() const { return retryTid != InvalidThreadID; } /** Sets the retry thread id, indicating that one of the LSQUnits |