O3PCU: Split loads and stores that cross cache line boundaries.

When each load or store is sent to the LSQ, we check whether it will cross a
cache line boundary and, if so, split it in two. This creates two TLB
translations and two memory requests. Care has to be taken if the first
packet of a split load is sent but the second blocks the cache. Similarly,
for a store, if the first packet cannot be sent, we must store the second
one somewhere to retry later.

This modifies the LSQSenderState class to record both packets in a split
load or store.

Finally, a new const variable, HasUnalignedMemAcc, is added to each ISA
to indicate whether unaligned memory accesses are allowed. This is used
throughout the changed code so that compiler can optimise away code dealing
with split requests for ISAs that don't need them.

1 files changed, 14 insertions, 8 deletions

diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh
index a0bae058c..7a7ea917f 100644
--- a/src/cpu/o3/lsq.hh
+++ b/src/cpu/o3/lsq.hh
@@ -270,15 +270,19 @@ class LSQ {
     void dumpInsts(ThreadID tid)
     { thread[tid].dumpInsts(); }
 
-    /** Executes a read operation, using the load specified at the load index. */
+    /** Executes a read operation, using the load specified at the load
+     * index.
+     */
     template <class T>
-    Fault read(RequestPtr req, T &data, int load_idx);
+    Fault read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
+               T &data, int load_idx);
 
     /** Executes a store operation, using the store specified at the store
-     *   index.
+     * index.
      */
     template <class T>
-    Fault write(RequestPtr req, T &data, int store_idx);
+    Fault write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
+                T &data, int store_idx);
 
     /** The CPU pointer. */
     O3CPU *cpu;
@@ -369,21 +373,23 @@ class LSQ {
 template <class Impl>
 template <class T>
 Fault
-LSQ<Impl>::read(RequestPtr req, T &data, int load_idx)
+LSQ<Impl>::read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
+                T &data, int load_idx)
 {
     ThreadID tid = req->threadId();
 
-    return thread[tid].read(req, data, load_idx);
+    return thread[tid].read(req, sreqLow, sreqHigh, data, load_idx);
 }
 
 template <class Impl>
 template <class T>
 Fault
-LSQ<Impl>::write(RequestPtr req, T &data, int store_idx)
+LSQ<Impl>::write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
+                 T &data, int store_idx)
 {
     ThreadID tid = req->threadId();
 
-    return thread[tid].write(req, data, store_idx);
+    return thread[tid].write(req, sreqLow, sreqHigh, data, store_idx);
 }
 
 #endif // __CPU_O3_LSQ_HH__