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| author | Binh Pham <binhpham@cs.rutgers.edu> | 2014-06-21 10:26:43 -0700 |
|---|---|---|
| committer | Binh Pham <binhpham@cs.rutgers.edu> | 2014-06-21 10:26:43 -0700 |
| commit | 0782d92286ded450b7e615fefbd5d6d5e738c8cd (patch) | |
| tree | f69fc67a0957740bab56e11ca9587834da3e18fa /src/cpu/o3/lsq.hh | |
| parent | fdb965f5c17d8866a63c206e1975460544d8eda9 (diff) | |
| download | gem5-0782d92286ded450b7e615fefbd5d6d5e738c8cd.tar.xz | |
o3: split load & store queue full cases in rename
Check for free entries in Load Queue and Store Queue separately to
avoid cases when load cannot be renamed due to full Store Queue and
vice versa.
This work was done while Binh was an intern at AMD Research.
Diffstat (limited to 'src/cpu/o3/lsq.hh')
| -rw-r--r-- | src/cpu/o3/lsq.hh | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh index 36ad75aed..e0ed05d7e 100644 --- a/src/cpu/o3/lsq.hh +++ b/src/cpu/o3/lsq.hh @@ -1,5 +1,6 @@ /* * Copyright (c) 2011-2012 ARM Limited + * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved * * The license below extends only to copyright in the software and shall @@ -204,11 +205,21 @@ class LSQ { int numStores(ThreadID tid) { return thread[tid].numStores(); } - /** Returns the number of free entries. */ - unsigned numFreeEntries(); + /** Returns the number of free load entries. */ + unsigned numFreeLoadEntries(); + + /** Returns the number of free store entries. */ + unsigned numFreeStoreEntries(); + /** Returns the number of free entries for a specific thread. */ unsigned numFreeEntries(ThreadID tid); + /** Returns the number of free entries in the LQ for a specific thread. */ + unsigned numFreeLoadEntries(ThreadID tid); + + /** Returns the number of free entries in the SQ for a specific thread. */ + unsigned numFreeStoreEntries(ThreadID tid); + /** Returns if the LSQ is full (either LQ or SQ is full). */ bool isFull(); /** |