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| author | Gabor Dozsa <gabor.dozsa@arm.com> | 2018-06-25 16:59:26 +0100 |
|---|---|---|
| committer | Gabor Dozsa <gabor.dozsa@arm.com> | 2019-02-22 12:16:20 +0000 |
| commit | 397d322b9952d264a99f025b026936aa7c2ed9cc (patch) | |
| tree | 5dff2562a62c9d7973186c1e16042c3108007c55 /src/cpu/o3/lsq.hh | |
| parent | 7d71f6641fcb660de0f003e2c028b464d7116ca1 (diff) | |
| download | gem5-397d322b9952d264a99f025b026936aa7c2ed9cc.tar.xz | |
cpu-o3: Add cache read ports limit to LSQ
This change introduces cache read ports to limit the number of
per-cycle loads. Previously only the number of per-cycle stores
could be limited.
Change-Id: I39bbd984056c5a696725ee2db462a55b2079e2d4
Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13517
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/cpu/o3/lsq.hh')
| -rw-r--r-- | src/cpu/o3/lsq.hh | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh index f576dd3f4..a6037b7f4 100644 --- a/src/cpu/o3/lsq.hh +++ b/src/cpu/o3/lsq.hh @@ -755,7 +755,7 @@ class LSQ int entryAmount(ThreadID num_threads); /** Ticks the LSQ. */ - void tick() { usedStorePorts = 0; } + void tick(); /** Inserts a load into the LSQ. */ void insertLoad(const DynInstPtr &load_inst); @@ -962,9 +962,9 @@ class LSQ /** Set D-cache blocked status */ void cacheBlocked(bool v); /** Is any store port available to use? */ - bool storePortAvailable() const; + bool cachePortAvailable(bool is_load) const; /** Another store port is in use */ - void storePortBusy(); + void cachePortBusy(bool is_load); protected: /** D-cache is blocked */ @@ -973,6 +973,10 @@ class LSQ int cacheStorePorts; /** The number of used cache ports in this cycle by stores. */ int usedStorePorts; + /** The number of cache ports available each cycle (loads only). */ + int cacheLoadPorts; + /** The number of used cache ports in this cycle by loads. */ + int usedLoadPorts; /** The LSQ policy for SMT mode. */ |