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| author | Giacomo Gabrielli <giacomo.gabrielli@arm.com> | 2019-10-02 15:43:47 +0100 |
|---|---|---|
| committer | Giacomo Gabrielli <giacomo.gabrielli@arm.com> | 2019-10-30 09:05:34 +0000 |
| commit | eef524d9ecf692875c899f112c4ddfdec03d7088 (patch) | |
| tree | 90cc5019a469b7311ec7d11575e478a7755b7ef1 /src/cpu/o3/lsq.hh | |
| parent | 94dfd6ac8289253386e6e20abc99761a0cbbe187 (diff) | |
| download | gem5-eef524d9ecf692875c899f112c4ddfdec03d7088.tar.xz | |
cpu-o3: Fix handling of some mem. order violations
This patch fixes the handling of memory order violations due to snoops
targeting out-of-order loads: the re-execution triggered in these cases
is achieved by raising a ReExec fault, but such a fault was not handled
correctly after the code changes introduced in changeset 46da8fb.
Change-Id: I2abe161a90468412f56cb28dcc92729326cba1cd
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21819
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Timothy Hayes <timothy.hayes@arm.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/cpu/o3/lsq.hh')
| -rw-r--r-- | src/cpu/o3/lsq.hh | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh index 6225c507d..ca92790b8 100644 --- a/src/cpu/o3/lsq.hh +++ b/src/cpu/o3/lsq.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2012, 2014, 2018 ARM Limited + * Copyright (c) 2011-2012, 2014, 2018-2019 ARM Limited * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved * @@ -623,6 +623,12 @@ class LSQ (isPartialFault() && isLoad())); } + void + setStateToFault() + { + setState(State::Fault); + } + /** * The LSQ entry is cleared */ |