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author | Iru Cai <mytbk920423@gmail.com> | 2019-02-28 17:07:16 +0800 |
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committer | Iru Cai <mytbk920423@gmail.com> | 2019-05-31 15:50:11 +0800 |
commit | a4c6e88d766858b675a7fd256df5a8b9a7e18ada (patch) | |
tree | a00f59eea3e87c31eb9efbce9f8d6f397ae16db2 /src/cpu/o3/lsq_impl.hh | |
parent | 866b200c202dded37fdd857a1a42ec149bd109c9 (diff) | |
download | gem5-a4c6e88d766858b675a7fd256df5a8b9a7e18ada.tar.xz |
import invisispec-1.0 source by Mengjia Yan
The original code is at https://github.com/mjyan0720/InvisiSpec-1.0
This code is rebased on upstream gem5 commit 866b200c, which features:
- rdtscp support
- some C++ code optimizations
- newer Linux kernel version number in SE mode
Diffstat (limited to 'src/cpu/o3/lsq_impl.hh')
-rw-r--r-- | src/cpu/o3/lsq_impl.hh | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh index 36bc17bc8..24066cd4b 100644 --- a/src/cpu/o3/lsq_impl.hh +++ b/src/cpu/o3/lsq_impl.hh @@ -292,6 +292,44 @@ LSQ<Impl>::writebackStores() } } +// [mengjia] +template<class Impl> +int +LSQ<Impl>::exposeLoads() +{ + list<ThreadID>::iterator threads = activeThreads->begin(); + list<ThreadID>::iterator end = activeThreads->end(); + + int exposedLoads = 0; + while (threads != end) { + ThreadID tid = *threads++; + + if (numLoadsToVLD(tid) > 0) { + DPRINTF(Writeback,"[tid:%i] Validate loads. %i loads " + "available for Validate.\n", tid, numLoadsToVLD(tid)); + } + + exposedLoads += thread[tid].exposeLoads(); + } + return exposedLoads; +} + + +// [mengjia] +template<class Impl> +void +LSQ<Impl>::updateVisibleState() +{ + list<ThreadID>::iterator threads = activeThreads->begin(); + list<ThreadID>::iterator end = activeThreads->end(); + + while (threads != end) { + ThreadID tid = *threads++; + + thread[tid].updateVisibleState(); + } +} + template<class Impl> bool LSQ<Impl>::violation() @@ -321,6 +359,7 @@ LSQ<Impl>::recvReqRetry() } } +// [InvisiSpec] Callback function for receiving a response template <class Impl> bool LSQ<Impl>::recvTimingResp(PacketPtr pkt) @@ -329,6 +368,17 @@ LSQ<Impl>::recvTimingResp(PacketPtr pkt) DPRINTF(LSQ, "Got error packet back for address: %#X\n", pkt->getAddr()); + // for expose or validate request, + // if the instruction is squashed, maybe the req has been deleted + if (pkt->isValidate() || pkt->isExpose()){ + if (!pkt->req){ + delete pkt; + return true; + } + DPRINTF(LSQ, "Receive an expose/validate response, idx=%d\n", + pkt->reqIdx); + } + thread[cpu->contextToThread(pkt->req->contextId())] .completeDataAccess(pkt); |