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authorGabe Black <gblack@eecs.umich.edu>2007-03-09 18:32:13 -0500
committerGabe Black <gblack@eecs.umich.edu>2007-03-09 18:32:13 -0500
commitdf1ea2cf05e41c0be33eeb9f91c3adfb985005c2 (patch)
tree0c9c9001bcedaa8ae986bbc638a92d1465cc89a9 /src/cpu/o3/lsq_impl.hh
parentf1e3e1c3053866f63f3826126260f43bf0c7d0c7 (diff)
parentdc4d47bad4f95501ebd144dc4aa53aa17563abcc (diff)
downloadgem5-df1ea2cf05e41c0be33eeb9f91c3adfb985005c2.tar.xz
Merge zizzer.eecs.umich.edu:/bk/newmem
into zower.eecs.umich.edu:/home/gblack/m5/newmem-statetrace --HG-- extra : convert_revision : 82a956ffc1bedb2c0d05c4ea3469f843f559a475
Diffstat (limited to 'src/cpu/o3/lsq_impl.hh')
-rw-r--r--src/cpu/o3/lsq_impl.hh13
1 files changed, 13 insertions, 0 deletions
diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index fb738f7c9..d4994fcb7 100644
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -34,6 +34,19 @@
#include "cpu/o3/lsq.hh"
+template<class Impl>
+void
+LSQ<Impl>::DcachePort::setPeer(Port *port)
+{
+ Port::setPeer(port);
+
+#if FULL_SYSTEM
+ // Update the ThreadContext's memory ports (Functional/Virtual
+ // Ports)
+ lsq->updateMemPorts();
+#endif
+}
+
template <class Impl>
Tick
LSQ<Impl>::DcachePort::recvAtomic(PacketPtr pkt)