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author | Mitch Hayenga <mitch.hayenga@arm.com> | 2014-09-03 07:42:39 -0400 |
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committer | Mitch Hayenga <mitch.hayenga@arm.com> | 2014-09-03 07:42:39 -0400 |
commit | 4f13f676aa71efaaae2fcd2587cf032a1d70f774 (patch) | |
tree | 1a8dec232d4bd77df2e773e824510959c643d091 /src/cpu/o3/lsq_impl.hh | |
parent | 283935a6f0a17afe4574cc3c50c043515c866dfa (diff) | |
download | gem5-4f13f676aa71efaaae2fcd2587cf032a1d70f774.tar.xz |
cpu: Fix cache blocked load behavior in o3 cpu
This patch fixes the load blocked/replay mechanism in the o3 cpu. Rather than
flushing the entire pipeline, this patch replays loads once the cache becomes
unblocked.
Additionally, deferred memory instructions (loads which had conflicting stores),
when replayed would not respect the number of functional units (only respected
issue width). This patch also corrects that.
Improvements over 20% have been observed on a microbenchmark designed to
exercise this behavior.
Diffstat (limited to 'src/cpu/o3/lsq_impl.hh')
-rw-r--r-- | src/cpu/o3/lsq_impl.hh | 23 |
1 files changed, 6 insertions, 17 deletions
diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh index 6e605b6a0..5d50b98ea 100644 --- a/src/cpu/o3/lsq_impl.hh +++ b/src/cpu/o3/lsq_impl.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2012 ARM Limited + * Copyright (c) 2011-2012, 2014 ARM Limited * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved * @@ -62,8 +62,7 @@ LSQ<Impl>::LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params) : cpu(cpu_ptr), iewStage(iew_ptr), LQEntries(params->LQEntries), SQEntries(params->SQEntries), - numThreads(params->numThreads), - retryTid(-1) + numThreads(params->numThreads) { assert(numThreads > 0 && numThreads <= Impl::MaxThreads); @@ -175,11 +174,6 @@ LSQ<Impl>::isDrained() const drained = false; } - if (retryTid != InvalidThreadID) { - DPRINTF(Drain, "Not drained, the LSQ has blocked the caches.\n"); - drained = false; - } - return drained; } @@ -338,16 +332,11 @@ template <class Impl> void LSQ<Impl>::recvRetry() { - if (retryTid == InvalidThreadID) - { - //Squashed, so drop it - return; + iewStage->cacheUnblocked(); + + for (ThreadID tid : *activeThreads) { + thread[tid].recvRetry(); } - int curr_retry_tid = retryTid; - // Speculatively clear the retry Tid. This will get set again if - // the LSQUnit was unable to complete its access. - retryTid = -1; - thread[curr_retry_tid].recvRetry(); } template <class Impl> |