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| author | Mitch Hayenga <mitch.hayenga@arm.com> | 2016-04-07 09:30:20 -0500 |
|---|---|---|
| committer | Mitch Hayenga <mitch.hayenga@arm.com> | 2016-04-07 09:30:20 -0500 |
| commit | c75ff71139d6358678835cca63e35d1135eaf466 (patch) | |
| tree | 0811177db4dca4a237b8e5d7dd65f8ec155cb14e /src/cpu/o3/lsq_impl.hh | |
| parent | d99deff8ea296fd28b48da08aba577a1e7dfc01b (diff) | |
| download | gem5-c75ff71139d6358678835cca63e35d1135eaf466.tar.xz | |
mem: Remove threadId from memory request class
In general, the ThreadID parameter is unnecessary in the memory system
as the ContextID is what is used for the purposes of locks/wakeups.
Since we allocate sequential ContextIDs for each thread on MT-enabled
CPUs, ThreadID is unnecessary as the CPUs can identify the requesting
thread through sideband info (SenderState / LSQ entries) or ContextID
offset from the base ContextID for a cpu.
This is a re-spin of 20264eb after the revert (bd1c6789) and includes
some fixes of that commit.
Diffstat (limited to 'src/cpu/o3/lsq_impl.hh')
| -rw-r--r-- | src/cpu/o3/lsq_impl.hh | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh index 06467243d..9080907fe 100644 --- a/src/cpu/o3/lsq_impl.hh +++ b/src/cpu/o3/lsq_impl.hh @@ -347,7 +347,8 @@ LSQ<Impl>::recvTimingResp(PacketPtr pkt) DPRINTF(LSQ, "Got error packet back for address: %#X\n", pkt->getAddr()); - thread[pkt->req->threadId()].completeDataAccess(pkt); + thread[cpu->contextToThread(pkt->req->contextId())] + .completeDataAccess(pkt); if (pkt->isInvalidate()) { // This response also contains an invalidate; e.g. this can be the case |