Merge zizzer:/bk/newmem

into  zeep.eecs.umich.edu:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : c8670f1a39d6826870ca0934587f4cc71c94b0ab

1 files changed, 6 insertions, 6 deletions

diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index 3de581519..cef6e0a2e 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -61,7 +61,7 @@ class LSQUnit {
     typedef TheISA::IntReg IntReg;
   public:
     typedef typename Impl::Params Params;
-    typedef typename Impl::FullCPU FullCPU;
+    typedef typename Impl::O3CPU O3CPU;
     typedef typename Impl::DynInstPtr DynInstPtr;
     typedef typename Impl::CPUPol::IEW IEW;
     typedef typename Impl::CPUPol::IssueStruct IssueStruct;
@@ -81,7 +81,7 @@ class LSQUnit {
     void regStats();
 
     /** Sets the CPU pointer. */
-    void setCPU(FullCPU *cpu_ptr);
+    void setCPU(O3CPU *cpu_ptr);
 
     /** Sets the IEW stage pointer. */
     void setIEW(IEW *iew_ptr)
@@ -232,7 +232,7 @@ class LSQUnit {
 
   private:
     /** Pointer to the CPU. */
-    FullCPU *cpu;
+    O3CPU *cpu;
 
     /** Pointer to the IEW stage. */
     IEW *iewStage;
@@ -249,13 +249,13 @@ class LSQUnit {
     {
       protected:
         /** Pointer to CPU. */
-        FullCPU *cpu;
+        O3CPU *cpu;
         /** Pointer to LSQ. */
         LSQUnit *lsq;
 
       public:
         /** Default constructor. */
-        DcachePort(FullCPU *_cpu, LSQUnit *_lsq)
+        DcachePort(O3CPU *_cpu, LSQUnit *_lsq)
             : Port(_lsq->name() + "-dport"), cpu(_cpu), lsq(_lsq)
         { }
 
@@ -527,7 +527,7 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
     // at the head of the LSQ and are ready to commit (at the head of the ROB
     // too).
     if (req->getFlags() & UNCACHEABLE &&
-        (load_idx != loadHead || !load_inst->reachedCommit)) {
+        (load_idx != loadHead || !load_inst->isAtCommit())) {
         iewStage->rescheduleMemInst(load_inst);
         ++lsqRescheduledLoads;
         return TheISA::genMachineCheckFault();