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author | Iru Cai <mytbk920423@gmail.com> | 2019-04-17 10:54:51 +0800 |
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committer | Iru Cai <mytbk920423@gmail.com> | 2019-05-31 16:03:29 +0800 |
commit | 50cdd2ccbe4e00f6768fc302ba3ef70fc4cb9170 (patch) | |
tree | f37742915e6fc53d07b74c65c5d454def21ae0a7 /src/cpu/o3/lsq_unit.hh | |
parent | 3d837e922175e0d9cfdea8c94a75f9e7178576d6 (diff) | |
download | gem5-50cdd2ccbe4e00f6768fc302ba3ef70fc4cb9170.tar.xz |
add a trackBranch option
Diffstat (limited to 'src/cpu/o3/lsq_unit.hh')
-rw-r--r-- | src/cpu/o3/lsq_unit.hh | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh index c512ef819..fbe5248f7 100644 --- a/src/cpu/o3/lsq_unit.hh +++ b/src/cpu/o3/lsq_unit.hh @@ -529,6 +529,7 @@ class LSQUnit { bool isFuturistic; bool allowSpecBuffHit; bool useIFT; + bool trackBranch; /* [mengjia] different schemes determine values of 4 variables. */ // Will also need how many read/write ports the Dcache has. Or keep track |