diff options
author | Kevin Lim <ktlim@umich.edu> | 2006-10-23 14:00:07 -0400 |
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committer | Kevin Lim <ktlim@umich.edu> | 2006-10-23 14:00:07 -0400 |
commit | 1926faac067c5ab01c0a925ccd5afc4d2bd6b83a (patch) | |
tree | 95ccd62ac972ef6c56932b4704633d957aa62a13 /src/cpu/o3/lsq_unit.hh | |
parent | 75ecd3be60d81fca759d34d9c8f0e4f500652aee (diff) | |
download | gem5-1926faac067c5ab01c0a925ccd5afc4d2bd6b83a.tar.xz |
Add in support for LL/SC in the O3 CPU. Needs to be fully tested.
src/cpu/base_dyn_inst.hh:
Extend BaseDynInst a little bit so it can be use as a TC as well (specifically for ll/sc code).
src/cpu/base_dyn_inst_impl.hh:
Add variable to track if the result of the instruction should be recorded.
src/cpu/o3/alpha/cpu_impl.hh:
Clear lock flag upon hwrei.
src/cpu/o3/lsq_unit.hh:
Use ISA specified handling of locked reads.
src/cpu/o3/lsq_unit_impl.hh:
Use ISA specified handling of locked writes.
--HG--
extra : convert_revision : 1f5c789c35deb4b016573c02af4aab60d726c0e5
Diffstat (limited to 'src/cpu/o3/lsq_unit.hh')
-rw-r--r-- | src/cpu/o3/lsq_unit.hh | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh index 11a02e7c7..00f24f98c 100644 --- a/src/cpu/o3/lsq_unit.hh +++ b/src/cpu/o3/lsq_unit.hh @@ -37,6 +37,7 @@ #include <queue> #include "arch/faults.hh" +#include "arch/locked_mem.hh" #include "config/full_system.hh" #include "base/hashmap.hh" #include "cpu/inst_seq.hh" @@ -510,8 +511,12 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx) #if FULL_SYSTEM if (req->isLocked()) { - cpu->lockAddr = req->getPaddr(); - cpu->lockFlag = true; + // Disable recording the result temporarily. Writing to misc + // regs normally updates the result, but this is not the + // desired behavior when handling store conditionals. + load_inst->recordResult = false; + TheISA::handleLockedRead(load_inst.get(), req); + load_inst->recordResult = true; } #endif |