diff options
| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-06-03 13:10:26 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-06-11 16:55:30 +0000 |
| commit | 2113b21996d086dab32b9fd388efe3df241bfbd2 (patch) | |
| tree | 26d944027f726dde3ec49b67538663ccc41bcad3 /src/cpu/o3/lsq_unit_impl.hh | |
| parent | 59505f7305cc3f3b7637233fd2d231bd7f561e80 (diff) | |
| download | gem5-2113b21996d086dab32b9fd388efe3df241bfbd2.tar.xz | |
misc: Substitute pointer to Request with aliased RequestPtr
Every usage of Request* in the code has been replaced with the
RequestPtr alias. This is a preparing patch for when RequestPtr will be
the typdefed to a smart pointer to Request rather then a raw pointer to
Request.
Change-Id: I73cbaf2d96ea9313a590cdc731a25662950cd51a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10995
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Diffstat (limited to 'src/cpu/o3/lsq_unit_impl.hh')
| -rw-r--r-- | src/cpu/o3/lsq_unit_impl.hh | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index ca6a7f399..e8e2c1853 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -831,7 +831,7 @@ LSQUnit<Impl>::writebackStores() DynInstPtr inst = storeQueue[storeWBIdx].inst; - Request *req = storeQueue[storeWBIdx].req; + RequestPtr req = storeQueue[storeWBIdx].req; RequestPtr sreqLow = storeQueue[storeWBIdx].sreqLow; RequestPtr sreqHigh = storeQueue[storeWBIdx].sreqHigh; |