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| author | Iru Cai <mytbk920423@gmail.com> | 2019-04-15 23:21:46 +0800 |
|---|---|---|
| committer | Iru Cai <mytbk920423@gmail.com> | 2019-04-15 23:21:46 +0800 |
| commit | 24b8aa03c307e799a8766952aeabac763f98010a (patch) | |
| tree | de8c6be5d4afb5fe9662bfe2a8f716e91f0788c0 /src/cpu/o3/lsq_unit_impl.hh | |
| parent | 08d003162e7a0bda11a5e4e96e0a6fa203f2c1f3 (diff) | |
| download | gem5-24b8aa03c307e799a8766952aeabac763f98010a.tar.xz | |
Add IFT debug flags
Diffstat (limited to 'src/cpu/o3/lsq_unit_impl.hh')
| -rw-r--r-- | src/cpu/o3/lsq_unit_impl.hh | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index a8ec0333f..79d913175 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -1055,7 +1055,7 @@ LSQUnit<Impl>::updateVisibleState() inst->readyToExpose(false); } else { /* set taint for dst registers */ - inst->taintDestRegs(true); + inst->taintDestRegs(true, "unsafe load"); /* if the load depends on tainted registers, set readyToExpose to false, otherwise set it to true */ |