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| author | Min Kyu Jeong <minkyu.jeong@arm.com> | 2010-12-07 16:19:57 -0800 |
|---|---|---|
| committer | Min Kyu Jeong <minkyu.jeong@arm.com> | 2010-12-07 16:19:57 -0800 |
| commit | 4bbdd6ceb2639fe21408ab211b7c4c7e53adb249 (patch) | |
| tree | b2fb062d30bc3b091d4390a671a2b0268e166121 /src/cpu/o3/lsq_unit_impl.hh | |
| parent | 21bfbd422cb9d043f88bd7f5ca9d4c72b97f9f33 (diff) | |
| download | gem5-4bbdd6ceb2639fe21408ab211b7c4c7e53adb249.tar.xz | |
O3: Support SWAP and predicated loads/store in ARM.
Diffstat (limited to 'src/cpu/o3/lsq_unit_impl.hh')
| -rw-r--r-- | src/cpu/o3/lsq_unit_impl.hh | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index 345d3ea69..807c0b527 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -531,10 +531,14 @@ LSQUnit<Impl>::executeStore(DynInstPtr &store_inst) Fault store_fault = store_inst->initiateAcc(); if (storeQueue[store_idx].size == 0) { - DPRINTF(LSQUnit,"Fault on Store PC %s, [sn:%lli],Size = 0\n", + DPRINTF(LSQUnit,"Fault on Store PC %s, [sn:%lli], Size = 0\n", store_inst->pcState(), store_inst->seqNum); return store_fault; + } else if (store_inst->readPredicate() == false) { + DPRINTF(LSQUnit, "Store [sn:%lli] not executed from predication\n", + store_inst->seqNum); + return store_fault; } assert(store_fault == NoFault); |