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authorBrad Beckmann <Brad.Beckmann@amd.com>2011-02-22 11:16:40 -0800
committerBrad Beckmann <Brad.Beckmann@amd.com>2011-02-22 11:16:40 -0800
commit63a25a56ccc93c24703fec87f830c833974e7060 (patch)
treea0f12244a32eb7da2963ca974ab49a993aee2cfc /src/cpu/o3/lsq_unit_impl.hh
parent8ea71c3907a411de9c203b45bfd6eab24e3ad849 (diff)
parent77eed184f529c4ccbef59ad2018d18ff3fbb54af (diff)
downloadgem5-63a25a56ccc93c24703fec87f830c833974e7060.tar.xz
m5: merged in hammer fix
Diffstat (limited to 'src/cpu/o3/lsq_unit_impl.hh')
-rw-r--r--src/cpu/o3/lsq_unit_impl.hh10
1 files changed, 9 insertions, 1 deletions
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index dd3604ffe..b5d337935 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -445,12 +445,16 @@ LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
Fault load_fault = NoFault;
DPRINTF(LSQUnit, "Executing load PC %s, [sn:%lli]\n",
- inst->pcState(),inst->seqNum);
+ inst->pcState(), inst->seqNum);
assert(!inst->isSquashed());
load_fault = inst->initiateAcc();
+ if (inst->isTranslationDelayed() &&
+ load_fault == NoFault)
+ return load_fault;
+
// If the instruction faulted or predicated false, then we need to send it
// along to commit without the instruction completing.
if (load_fault != NoFault || inst->readPredicate() == false) {
@@ -532,6 +536,10 @@ LSQUnit<Impl>::executeStore(DynInstPtr &store_inst)
Fault store_fault = store_inst->initiateAcc();
+ if (store_inst->isTranslationDelayed() &&
+ store_fault == NoFault)
+ return store_fault;
+
if (store_inst->readPredicate() == false)
store_inst->forwardOldRegs();