add IFT options

1 files changed, 20 insertions, 16 deletions

diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index e31532d48..7ac85654e 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -231,9 +231,10 @@ LSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params,
     }
     needsTSO = params->needsTSO;
     allowSpecBuffHit = params->allowSpecBuffHit;
+    useIFT = params->useIFT;
     cprintf("Info: simulation uses scheme: %s; "
-                "needsTSO=%d; allowSpecBuffHit=%d\n",
-                scheme, needsTSO, allowSpecBuffHit);
+            "needsTSO=%d; allowSpecBuffHit=%d; useIFT=%d\n",
+            scheme, needsTSO, allowSpecBuffHit, useIFT);
     // [mengjia] end of setting configuration variables
 
     resetState();
@@ -1042,30 +1043,33 @@ LSQUnit<Impl>::updateVisibleState()
                     }
                 }
                 inst->readyToExpose(true);
-            }else {
-#if 0 /* now an untainted USL can be safe */
-                if (inst->readyToExpose()){
+            } else {
+                if (!useIFT) {
+                  if (inst->readyToExpose()){
                     DPRINTF(LSQUnit, "The load can not be validated "
                             "[sn:%lli] PC %s\n",
-                        inst->seqNum, inst->pcState());
+                            inst->seqNum, inst->pcState());
                     assert(0);
                     //--loadsToVLD;
-                }
-#endif
-                /* set taint for dst registers */
-                inst->taintDestRegs(true);
-                /* if the load depends on tainted registers, set
-                   readyToExpose to false, otherwise set it to true
-                */
-                if (inst->srcTainted()) {
+                  }
+                  inst->readyToExpose(false);
+                } else {
+                  /* set taint for dst registers */
+                  inst->taintDestRegs(true);
+                  inst->isTainted = true;
+                  /* if the load depends on tainted registers, set
+                     readyToExpose to false, otherwise set it to true
+                  */
+                  if (inst->srcTainted()) {
                     DPRINTF(LSQUnit, "load inst [sn:%lli] %s not safe, set readyToExpose to false\n", inst->seqNum, inst->pcState());
                     inst->readyToExpose(false);
-                } else {
+                  } else {
                     DPRINTF(LSQUnit, "load inst [sn:%lli] %s is an unsafe speculated load, but source registers are not tainted.\n", inst->seqNum, inst->pcState());
                     if (!inst->readyToExpose() && inst->needPostFetch()) {
-                        ++loadsToVLD;
+                      ++loadsToVLD;
                     }
                     inst->readyToExpose(true);
+                  }
                 }
             }
             inst->fenceDelay(false);