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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2014-01-24 15:29:30 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2014-01-24 15:29:30 -0600 |
| commit | 90b1775a8f87834d4c27d4c98483bb7b1e5e9679 (patch) | |
| tree | 5c06b3e32bde9938dc977e1a59c288e87075b521 /src/cpu/o3/lsq_unit_impl.hh | |
| parent | 6bed6e0352a68723ea55017b3e09a8c279af11ec (diff) | |
| download | gem5-90b1775a8f87834d4c27d4c98483bb7b1e5e9679.tar.xz | |
cpu: Add support for instructions that zero cache lines.
Diffstat (limited to 'src/cpu/o3/lsq_unit_impl.hh')
| -rw-r--r-- | src/cpu/o3/lsq_unit_impl.hh | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index 7ec59e38d..322a6704a 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -816,9 +816,12 @@ LSQUnit<Impl>::writebackStores() storeQueue[storeWBIdx].committed = true; assert(!inst->memData); - inst->memData = new uint8_t[64]; + inst->memData = new uint8_t[req->getSize()]; - memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize()); + if (storeQueue[storeWBIdx].isAllZeros) + memset(inst->memData, 0, req->getSize()); + else + memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize()); MemCmd command = req->isSwap() ? MemCmd::SwapReq : |