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| author | Min Kyu Jeong <minkyu.jeong@arm.com> | 2010-08-23 11:18:42 -0500 |
|---|---|---|
| committer | Min Kyu Jeong <minkyu.jeong@arm.com> | 2010-08-23 11:18:42 -0500 |
| commit | d8d6b869a2f34b602cdc216660d08b9acba93d43 (patch) | |
| tree | b1bef84ccf7247b0822051a8a127da9dec71e164 /src/cpu/o3/lsq_unit_impl.hh | |
| parent | e6a0be648e9fdb4b882cfb5f3224d097817338bc (diff) | |
| download | gem5-d8d6b869a2f34b602cdc216660d08b9acba93d43.tar.xz | |
O3: Skipping mem-order violation check for uncachable loads.
Uncachable load is not executed until it reaches the head of the ROB,
hence cannot cause one.
Diffstat (limited to 'src/cpu/o3/lsq_unit_impl.hh')
| -rw-r--r-- | src/cpu/o3/lsq_unit_impl.hh | 18 |
1 files changed, 14 insertions, 4 deletions
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index 7330ba2ef..8aa7fe397 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -479,9 +479,14 @@ LSQUnit<Impl>::executeLoad(DynInstPtr &inst) // are quad word accesses. // @todo: Fix this, magic number being used here + + // @todo: Uncachable load is not executed until it reaches + // the head of the ROB. Once this if checks only the executed + // loads(as noted above), this check can be removed if (loadQueue[load_idx]->effAddrValid && - (loadQueue[load_idx]->effAddr >> 8) == - (inst->effAddr >> 8)) { + ((loadQueue[load_idx]->effAddr >> 8) + == (inst->effAddr >> 8)) && + !loadQueue[load_idx]->uncacheable()) { // A load incorrectly passed this load. Squash and refetch. // For now return a fault to show that it was unsuccessful. DynInstPtr violator = loadQueue[load_idx]; @@ -553,9 +558,14 @@ LSQUnit<Impl>::executeStore(DynInstPtr &store_inst) // are quad word accesses. // @todo: Fix this, magic number being used here + + // @todo: Uncachable load is not executed until it reaches + // the head of the ROB. Once this if checks only the executed + // loads(as noted above), this check can be removed if (loadQueue[load_idx]->effAddrValid && - (loadQueue[load_idx]->effAddr >> 8) == - (store_inst->effAddr >> 8)) { + ((loadQueue[load_idx]->effAddr >> 8) + == (store_inst->effAddr >> 8)) && + !loadQueue[load_idx]->uncacheable()) { // A load incorrectly passed this store. Squash and refetch. // For now return a fault to show that it was unsuccessful. DynInstPtr violator = loadQueue[load_idx]; |