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| author | Iru Cai <mytbk920423@gmail.com> | 2019-04-03 10:29:37 +0800 |
|---|---|---|
| committer | Iru Cai <mytbk920423@gmail.com> | 2019-04-03 10:55:39 +0800 |
| commit | f76b874533045543e56a69c1b5d75b34fbc8a888 (patch) | |
| tree | c7f2948cf916ff938a713b6856cec789cb5f6982 /src/cpu/o3/lsq_unit_impl.hh | |
| parent | b28522528109f87d9420e59a31cef88a045ed0e6 (diff) | |
| download | gem5-f76b874533045543e56a69c1b5d75b34fbc8a888.tar.xz | |
check loads using tainted registers, set USL dst as tainted
Diffstat (limited to 'src/cpu/o3/lsq_unit_impl.hh')
| -rw-r--r-- | src/cpu/o3/lsq_unit_impl.hh | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index 7462d4c84..14256e382 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -1043,6 +1043,7 @@ LSQUnit<Impl>::updateVisibleState() } inst->readyToExpose(true); }else { +#if 0 /* now an untainted USL can be safe */ if (inst->readyToExpose()){ DPRINTF(LSQUnit, "The load can not be validated " "[sn:%lli] PC %s\n", @@ -1050,7 +1051,19 @@ LSQUnit<Impl>::updateVisibleState() assert(0); //--loadsToVLD; } - inst->readyToExpose(false); +#endif + /* set taint for dst registers */ + inst->taintDestRegs(); + /* if the load depends on tainted registers, set + readyToExpose to false, otherwise set it to true + */ + if (inst->srcTainted()) { + DPRINTF(LSQUnit, "load inst [sn:%lli] %s not safe, set readyToExpose to false\n", inst->seqNum, inst->pcState()); + inst->readyToExpose(false); + } else { + DPRINTF(LSQUnit, "load inst [sn:%lli] %s is an unsafe speculated load, but source registers are not tainted.\n", inst->seqNum, inst->pcState()); + inst->readyToExpose(true); + } } inst->fenceDelay(false); } else { |