diff options
| author | Iru Cai <mytbk920423@gmail.com> | 2019-04-15 23:21:46 +0800 |
|---|---|---|
| committer | Iru Cai <mytbk920423@gmail.com> | 2019-05-31 16:03:29 +0800 |
| commit | e9d7833de3115201ee68b6f22a105abb511dc8c4 (patch) | |
| tree | 7db6dd4d63c60e35ebe7d7a3377679f6027f8de2 /src/cpu/o3/lsq_unit_impl.hh | |
| parent | 66db5f3f26cee684b0f078ca31e139ce30523f02 (diff) | |
| download | gem5-e9d7833de3115201ee68b6f22a105abb511dc8c4.tar.xz | |
Add IFT debug flags
Diffstat (limited to 'src/cpu/o3/lsq_unit_impl.hh')
| -rw-r--r-- | src/cpu/o3/lsq_unit_impl.hh | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index a8ec0333f..79d913175 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -1055,7 +1055,7 @@ LSQUnit<Impl>::updateVisibleState() inst->readyToExpose(false); } else { /* set taint for dst registers */ - inst->taintDestRegs(true); + inst->taintDestRegs(true, "unsafe load"); /* if the load depends on tainted registers, set readyToExpose to false, otherwise set it to true */ |