diff options
| author | Min Kyu Jeong <minkyu.jeong@arm.com> | 2010-08-23 11:18:40 -0500 |
|---|---|---|
| committer | Min Kyu Jeong <minkyu.jeong@arm.com> | 2010-08-23 11:18:40 -0500 |
| commit | 43c938d23e2b28c7190bd10c470c452676f5cb9d (patch) | |
| tree | d6176dc000ff7dd2d0789ae92f6318791e3e6f27 /src/cpu/o3/lsq_unit_impl.hh | |
| parent | 5f91ec3f4618dad8d36efbf8b5a5112a1ce0d1b7 (diff) | |
| download | gem5-43c938d23e2b28c7190bd10c470c452676f5cb9d.tar.xz | |
O3: Handle loads when the destination is the PC.
For loads that PC is the destination, check if the load
was mispredicted again when the value being loaded returns from memory
Diffstat (limited to 'src/cpu/o3/lsq_unit_impl.hh')
| -rw-r--r-- | src/cpu/o3/lsq_unit_impl.hh | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index dddfb7e1b..9e6bbe92f 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -989,6 +989,9 @@ LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt) iewStage->instToCommit(inst); iewStage->activityThisCycle(); + + // see if this load changed the PC + iewStage->checkMisprediction(inst); } template <class Impl> |